llvm-6502/test/CodeGen/Hexagon/dualstore.ll
Jyotsna Verma ee0ef13eba Hexagon: Add encoding bits to the TFR64 instructions.
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 18:42:28 +00:00

18 lines
540 B
LLVM

; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s
; Check that we generate dual stores in one packet in V4
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##500000
; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##100000
; CHECK-NEXT: }
@Reg = global i32 0, align 4
define i32 @main() nounwind {
entry:
%number= alloca i32, align 4
store i32 500000, i32* %number, align 4
%number1= alloca i32, align 4
store i32 100000, i32* %number1, align 4
ret i32 0
}