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https://github.com/c64scene-ar/llvm-6502.git
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c0f6420b96
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15635 91177308-0d34-0410-b5e6-96231b3b80d8
118 lines
4.0 KiB
C++
118 lines
4.0 KiB
C++
//===-- PPC64TargetMachine.cpp - Define TargetMachine for AIX/PowerPC ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "PowerPC.h"
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#include "PPC64JITInfo.h"
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#include "PPC64TargetMachine.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/IntrinsicLowering.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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const std::string PPC64 = "AIX/PowerPC";
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// Register the target
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RegisterTarget<PPC64TargetMachine>
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X("powerpc-aix", " AIX/PowerPC (experimental)");
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}
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/// PPC64TargetMachine ctor
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///
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PPC64TargetMachine::PPC64TargetMachine(const Module &M, IntrinsicLowering *IL)
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// FIXME: this is wrong!
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: PowerPCTargetMachine(PPC64, IL,
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TargetData(PPC64,false,8,4,4,4,4,4,2,1,4),
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TargetFrameInfo(TargetFrameInfo::StackGrowsDown,16,-4),
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PPC64JITInfo(*this)) {}
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/// addPassesToEmitAssembly - Add passes to the specified pass manager
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/// to implement a static compiler for this target.
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///
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bool PPC64TargetMachine::addPassesToEmitAssembly(PassManager &PM,
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std::ostream &Out) {
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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PM.add(createLowerConstantExpressionsPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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// FIXME: instruction selector!
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//PM.add(createPPCSimpleInstructionSelector(*this));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createRegisterAllocator());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// I want a PowerPC specific prolog/epilog code inserter so I can put the
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// fills/spills in the right spots.
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//PM.add(createPowerPCPEI());
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// Must run branch selection immediately preceding the printer
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//PM.add(createPPCBranchSelectionPass());
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//PM.add(createPPC32AsmPrinterPass(Out, *this));
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PM.add(createMachineCodeDeleter());
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return false;
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}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target.
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///
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void PPC64JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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PM.add(createLowerConstantExpressionsPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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// FIXME: ISel
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//PM.add(createPPCSimpleInstructionSelector(TM));
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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}
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unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) {
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if (M.getEndianness() == Module::BigEndian &&
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M.getPointerSize() == Module::Pointer64)
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return 10; // Direct match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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