llvm-6502/lib/Target/Sparc
2011-07-07 07:07:08 +00:00
..
TargetInfo
CMakeLists.txt Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. 2011-07-01 22:36:09 +00:00
DelaySlotFiller.cpp - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 2011-06-28 19:10:37 +00:00
FPMover.cpp
Makefile Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. 2011-07-01 22:36:09 +00:00
README.txt
Sparc.h Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc 2011-06-28 20:07:07 +00:00
Sparc.td
SparcAsmPrinter.cpp
SparcCallingConv.td
SparcFrameLowering.cpp
SparcFrameLowering.h
SparcInstrFormats.td
SparcInstrInfo.cpp Hide the call to InitMCInstrInfo into tblgen generated ctor. 2011-07-01 17:57:27 +00:00
SparcInstrInfo.h Hide the call to InitMCInstrInfo into tblgen generated ctor. 2011-07-01 17:57:27 +00:00
SparcInstrInfo.td
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp Remove getRegClassForInlineAsmConstraint from sparc. 2011-06-29 18:53:10 +00:00
SparcISelLowering.h Remove getRegClassForInlineAsmConstraint from sparc. 2011-06-29 18:53:10 +00:00
SparcMachineFunctionInfo.h
SparcMCAsmInfo.cpp
SparcMCAsmInfo.h
SparcRegisterInfo.cpp Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. 2011-06-28 21:14:33 +00:00
SparcRegisterInfo.h Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc 2011-06-27 18:32:37 +00:00
SparcRegisterInfo.td Use set operations instead of plain lists to enumerate register classes. 2011-06-15 23:28:14 +00:00
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp Compute feature bits at time of MCSubtargetInfo initialization. 2011-07-07 07:07:08 +00:00
SparcSubtarget.h Compute feature bits at time of MCSubtargetInfo initialization. 2011-07-07 07:07:08 +00:00
SparcTargetMachine.cpp Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to 2011-06-30 01:53:36 +00:00
SparcTargetMachine.h Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to 2011-06-30 01:53:36 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support