Evan Cheng 15213b77cf SIGN_EXTEND_INREG requires one extra operand, a ValueType node. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35350 91177308-0d34-0410-b5e6-96231b3b80d8		2007-03-26 07:12:51 +00:00
..
CallingConvLower.cpp	add methods for analysis of call results and return nodes.	2007-02-28 07:09:40 +00:00
DAGCombiner.cpp	SIGN_EXTEND_INREG requires one extra operand, a ValueType node.	2007-03-26 07:12:51 +00:00
LegalizeDAG.cpp	don't rely on ADL	2007-03-24 17:37:03 +00:00
Makefile	For PR780:	2006-07-26 16:18:00 +00:00
ScheduleDAG.cpp	Fix some VC++ warnings.	2007-03-20 20:43:18 +00:00
ScheduleDAGList.cpp	switch the sched unit map over to use a DenseMap instead of std::map. This	2007-02-03 01:34:13 +00:00
ScheduleDAGRRList.cpp	Estimate a cost using the possible number of scratch registers required and use	2007-03-14 22:43:40 +00:00
ScheduleDAGSimple.cpp	switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This	2007-02-04 08:47:20 +00:00
SelectionDAG.cpp	fold away addc nodes when we know there cannot be a carry-out.	2007-03-04 20:40:38 +00:00
SelectionDAGISel.cpp	First step of switch lowering refactoring: perform worklist-driven	2007-03-25 15:07:15 +00:00
SelectionDAGPrinter.cpp	Removing even more <iostream> includes.	2006-12-07 20:04:42 +00:00
TargetLowering.cpp	implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll	2007-03-25 04:35:41 +00:00