Tim Northover 0adfdedacb Fix 64-bit atomic operations in Thumb mode. ... The ARM and Thumb variants of LDREXD and STREXD have different constraints and take different operands. Previously the code expanding atomic operations didn't take this into account and asserted in Thumb mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173780 91177308-0d34-0410-b5e6-96231b3b80d8		2013-01-29 09:06:13 +00:00
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ARM	Fix 64-bit atomic operations in Thumb mode.	2013-01-29 09:06:13 +00:00
CPP
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
Hexagon	Add indexed load/store instructions for offset validation check.	2013-01-17 18:42:37 +00:00
MBlaze
Mips	[mips] Set flag neverHasSideEffects flag on some of the floating point instructions.	2013-01-25 00:20:39 +00:00
MSP430
NVPTX
PowerPC	This patch addresses bug 15031.	2013-01-28 18:36:58 +00:00
R600
SI
SPARC
Thumb
Thumb2	FileCheck-ify some grep tests	2013-01-25 22:11:46 +00:00
X86	When the legalizer is splitting vector shifts, the result may not have the right shift amount type.	2013-01-27 11:19:11 +00:00
XCore