llvm-6502/test/CodeGen
Jakob Stoklund Olesen 027c32a14e Use the right register class for LDRrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-20 06:38:47 +00:00
..
ARM Transfer memory operands to the right instruction. 2012-05-20 06:38:42 +00:00
CellSPU
CPP
Generic change the objectsize intrinsic signature: add a 3rd parameter to denote the maximum runtime performance penalty that the user is willing to accept. 2012-05-09 15:52:43 +00:00
Hexagon Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
MBlaze
Mips Add support for the 'd' mips inline asm output modifier. 2012-05-19 00:51:56 +00:00
MSP430
NVPTX
PowerPC Remove -join-physregs from the test suite. 2012-05-17 23:44:19 +00:00
PTX
SPARC
Thumb
Thumb2 Use the right register class for LDRrs. 2012-05-20 06:38:47 +00:00
X86 Properly constrain register classes for sub-registers. 2012-05-20 06:38:37 +00:00
XCore