llvm-6502/lib/CodeGen
Evan Cheng 02bee85a70 New entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48908 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-28 06:34:23 +00:00
..
SelectionDAG Implement LegalizeTypes support for softfloat LOAD. 2008-03-27 20:23:40 +00:00
AsmPrinter.cpp Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 2008-03-15 00:03:38 +00:00
BranchFolding.cpp Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries. 2008-02-28 00:43:03 +00:00
Collector.cpp
CollectorMetadata.cpp
Collectors.cpp
DwarfWriter.cpp Fix a bug in Darwin EH: FDE->CIE pointer must 2008-03-26 23:31:39 +00:00
ELFWriter.cpp Use PassManagerBase instead of FunctionPassManager for functions 2008-03-11 22:29:46 +00:00
ELFWriter.h Don't include <map> in Pass.h, which doesn't need it. This requires 2008-03-21 23:51:57 +00:00
IfConversion.cpp Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries. 2008-02-28 00:43:03 +00:00
IntrinsicLowering.cpp
LiveInterval.cpp
LiveIntervalAnalysis.cpp Remove isImplicitDef TargetInstrDesc flag. 2008-03-15 00:19:36 +00:00
LiveVariables.cpp Fix live variables issues: 2008-03-19 00:52:20 +00:00
LLVMTargetMachine.cpp Avoid outputing spaces at the ends of lines. 2008-03-25 21:38:12 +00:00
LoopAligner.cpp Fix PR2112: don't run loop aligner if target doesn't have a TargetLowering object. 2008-02-29 17:52:15 +00:00
LowerSubregs.cpp Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. 2008-03-16 03:12:01 +00:00
MachineBasicBlock.cpp Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries. 2008-02-28 00:43:03 +00:00
MachineDominators.cpp
MachineFunction.cpp
MachineInstr.cpp detabify llvm, patch by Mike Stump! 2008-03-20 01:22:40 +00:00
MachineLICM.cpp Minor cleanup. No functionality change. 2008-03-10 08:13:01 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp A quick nm audit turned up several fixed tables and objects that were 2008-03-25 21:45:14 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp Refactor some code out of MachineSink into a MachineInstr query. 2008-03-13 00:44:09 +00:00
MachOWriter.cpp Use PassManagerBase instead of FunctionPassManager for functions 2008-03-11 22:29:46 +00:00
MachOWriter.h Don't include <map> in Pass.h, which doesn't need it. This requires 2008-03-21 23:51:57 +00:00
Makefile
OcamlCollector.cpp
Passes.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
PHIElimination.cpp Refactor code. Remove duplicated functions that basically do the same thing as 2008-03-05 00:59:57 +00:00
PhysRegTracker.h
PostRASchedulerList.cpp
PrologEpilogInserter.cpp detabify llvm, patch by Mike Stump! 2008-03-20 01:22:40 +00:00
PseudoSourceValue.cpp A quick nm audit turned up several fixed tables and objects that were 2008-03-25 21:45:14 +00:00
README.txt New entry. 2008-03-28 06:34:23 +00:00
RegAllocBigBlock.cpp
RegAllocLinearScan.cpp Add an assertion to catch register of illegal class. 2008-03-24 23:28:21 +00:00
RegAllocLocal.cpp Refactor code. Remove duplicated functions that basically do the same thing as 2008-03-05 00:59:57 +00:00
RegAllocSimple.cpp Don't include <map> in Pass.h, which doesn't need it. This requires 2008-03-21 23:51:57 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp Something that kills a super-register also 2008-03-07 23:45:15 +00:00
ShadowStackCollector.cpp
SimpleRegisterCoalescing.cpp One more coalescer fix wrt deadness propagation. 2008-03-26 20:15:49 +00:00
SimpleRegisterCoalescing.h Rewrite code that propagate isDead information after a dead copy is coalesced. This remove some ugly spaghetti code and fixed a number of subtle bugs. 2008-03-18 08:26:47 +00:00
StrongPHIElimination.cpp Dead PHI instructions need to be handled specially. 2008-03-26 03:03:23 +00:00
TargetInstrInfoImpl.cpp
TwoAddressInstructionPass.cpp Fix a memory bug: increment an iterator of a deleted machine instr. 2008-03-27 01:27:25 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Avoid commuting a def MI in order to coalesce a copy instruction away if any use of the same val# is a copy instruction that has already been coalesced. 2008-03-26 19:03:01 +00:00
VirtRegMap.h Fix typos in comments. 2008-03-12 20:50:04 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
	ldr r3, [sp, #+4]
	add r3, r3, #3
	ldr r2, [sp, #+8]
	add r2, r2, #2
	ldr r1, [sp, #+4]  <==
	add r1, r1, #1
	ldr r0, [sp, #+4]
	add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Avoid issuing copies of TargetInstrInfo::implicit_def.