Tanya Lattner 0433b21c98 Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8		2011-04-07 15:24:20 +00:00
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Alpha	If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.	2010-12-06 22:39:26 +00:00
ARM	Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.	2011-04-07 15:24:20 +00:00
Blackfin	Don't completely eliminate identity copies that also modify super register liveness.	2011-03-31 17:55:25 +00:00
CBackend
CellSPU	Roll r127459 back in:	2011-03-11 21:52:04 +00:00
CPP
Generic	ARM doesn't support byval yet. XFAIL this test until it does.	2011-04-05 17:16:21 +00:00
MBlaze	fix visitShift to properly zero extend the shift amount if the provided operand	2011-02-13 09:02:52 +00:00
Mips	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
MSP430	Enhance ComputeMaskedBits to know that aligned frameindexes	2011-02-13 22:25:43 +00:00
PowerPC	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
PTX	ptx: support setp's 4-operand format	2011-04-02 08:51:39 +00:00
SPARC	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
SystemZ	Fix SystemZ tests	2011-03-31 23:02:12 +00:00
Thumb	Fix Thumb and Thumb2 tests to be register allocator independent.	2011-03-31 23:31:50 +00:00
Thumb2	Fix Thumb and Thumb2 tests to be register allocator independent.	2011-03-31 23:31:50 +00:00
X86	Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.	2011-04-05 21:40:37 +00:00
XCore	Fix Mips, Sparc, and XCore tests that were dependent on register allocation.	2011-03-31 18:42:43 +00:00