Scott Michel 045a14503f CellSPU: ... (a) Slight rethink on i64 zero/sign/any extend code - use a shuffle to directly zero-extend i32 to i64, but use rotates and shifts for sign extension. Also ensure unified register consistency. (b) Add new test harness for i64 operations: i64ops.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59970 91177308-0d34-0410-b5e6-96231b3b80d8		2008-11-24 18:20:46 +00:00
..
Alpha	Correct some thinkos in the expansion of ADD/SUB	2008-11-12 08:23:26 +00:00
ARM	- Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction.	2008-11-20 02:32:35 +00:00
CBackend	Fix PR2907 by digging through constant expressions to find FP constants that	2008-10-22 04:53:16 +00:00
CellSPU	CellSPU:	2008-11-24 18:20:46 +00:00
CPP
Generic	Test add-with-overflow with fast ISel.	2008-11-24 05:23:38 +00:00
IA64
Mips	Fix PR2667: add soft float support for sint_to_fp/uint_to_fp	2008-11-10 17:36:26 +00:00
PowerPC	Remove these, which test for optimizations that	2008-11-17 18:57:45 +00:00
SPARC
X86	Add support for rematerialization in pre-alloc-splitting.	2008-11-19 04:28:29 +00:00
XCore	Reapply r59464, this time using the correct type	2008-11-18 09:15:03 +00:00