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053a211983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172992 91177308-0d34-0410-b5e6-96231b3b80d8
216 lines
8.9 KiB
C++
216 lines
8.9 KiB
C++
//===- llvm/Analysis/TargetTransformInfo.h ----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass exposes codegen information to IR-level passes. Every
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// transformation that uses codegen information is broken into three parts:
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// 1. The IR-level analysis pass.
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// 2. The IR-level transformation interface which provides the needed
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// information.
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// 3. Codegen-level implementation which uses target-specific hooks.
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//
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// This file defines #2, which is the interface that IR-level transformations
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// use for querying the codegen.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
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#define LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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/// TargetTransformInfo - This pass provides access to the codegen
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/// interfaces that are needed for IR-level transformations.
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class TargetTransformInfo {
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protected:
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/// \brief The TTI instance one level down the stack.
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///
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/// This is used to implement the default behavior all of the methods which
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/// is to delegate up through the stack of TTIs until one can answer the
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/// query.
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TargetTransformInfo *PrevTTI;
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/// \brief The top of the stack of TTI analyses available.
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///
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/// This is a convenience routine maintained as TTI analyses become available
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/// that complements the PrevTTI delegation chain. When one part of an
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/// analysis pass wants to query another part of the analysis pass it can use
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/// this to start back at the top of the stack.
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TargetTransformInfo *TopTTI;
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/// All pass subclasses must in their initializePass routine call
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/// pushTTIStack with themselves to update the pointers tracking the previous
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/// TTI instance in the analysis group's stack, and the top of the analysis
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/// group's stack.
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void pushTTIStack(Pass *P);
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/// All pass subclasses must in their finalizePass routine call popTTIStack
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/// to update the pointers tracking the previous TTI instance in the analysis
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/// group's stack, and the top of the analysis group's stack.
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void popTTIStack();
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/// All pass subclasses must call TargetTransformInfo::getAnalysisUsage.
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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public:
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/// This class is intended to be subclassed by real implementations.
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virtual ~TargetTransformInfo() = 0;
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/// \name Scalar Target Information
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/// @{
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/// \brief Flags indicating the kind of support for population count.
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///
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/// Compared to the SW implementation, HW support is supposed to
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/// significantly boost the performance when the population is dense, and it
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/// may or may not degrade performance if the population is sparse. A HW
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/// support is considered as "Fast" if it can outperform, or is on a par
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/// with, SW implementaion when the population is sparse; otherwise, it is
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/// considered as "Slow".
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enum PopcntSupportKind {
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PSK_Software,
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PSK_SlowHardware,
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PSK_FastHardware
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};
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/// isLegalAddImmediate - Return true if the specified immediate is legal
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/// add immediate, that is the target has add instructions which can add
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/// a register with the immediate without having to materialize the
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/// immediate into a register.
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virtual bool isLegalAddImmediate(int64_t Imm) const;
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/// isLegalICmpImmediate - Return true if the specified immediate is legal
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/// icmp immediate, that is the target has icmp instructions which can compare
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/// a register against the immediate without having to materialize the
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/// immediate into a register.
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virtual bool isLegalICmpImmediate(int64_t Imm) const;
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/// isLegalAddressingMode - Return true if the addressing mode represented by
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/// AM is legal for this target, for a load/store of the specified type.
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/// The type may be VoidTy, in which case only return true if the addressing
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/// mode is legal for a load/store of any legal type.
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/// TODO: Handle pre/postinc as well.
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virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
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int64_t BaseOffset, bool HasBaseReg,
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int64_t Scale) const;
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/// isTruncateFree - Return true if it's free to truncate a value of
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/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
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/// register EAX to i16 by referencing its sub-register AX.
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virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
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/// Is this type legal.
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virtual bool isTypeLegal(Type *Ty) const;
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/// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
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virtual unsigned getJumpBufAlignment() const;
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/// getJumpBufSize - returns the target's jmp_buf size in bytes.
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virtual unsigned getJumpBufSize() const;
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/// shouldBuildLookupTables - Return true if switches should be turned into
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/// lookup tables for the target.
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virtual bool shouldBuildLookupTables() const;
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/// getPopcntSupport - Return hardware support for population count.
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virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
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/// getIntImmCost - Return the expected cost of materializing the given
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/// integer immediate of the specified type.
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virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
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/// @}
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/// \name Vector Target Information
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/// @{
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/// \brief The various kinds of shuffle patterns for vector queries.
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enum ShuffleKind {
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SK_Broadcast, ///< Broadcast element 0 to all other elements.
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SK_Reverse, ///< Reverse the order of the vector.
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SK_InsertSubvector, ///< InsertSubvector. Index indicates start offset.
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SK_ExtractSubvector ///< ExtractSubvector Index indicates start offset.
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};
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/// \return The number of scalar or vector registers that the target has.
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/// If 'Vectors' is true, it returns the number of vector registers. If it is
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/// set to false, it returns the number of scalar registers.
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virtual unsigned getNumberOfRegisters(bool Vector) const;
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/// \return The width of the largest scalar or vector register type.
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virtual unsigned getRegisterBitWidth(bool Vector) const;
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/// \return The maximum unroll factor that the vectorizer should try to
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/// perform for this target. This number depends on the level of parallelism
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/// and the number of execution units in the CPU.
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virtual unsigned getMaximumUnrollFactor() const;
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/// \return The expected cost of arithmetic ops, such as mul, xor, fsub, etc.
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virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
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/// \return The cost of a shuffle instruction of kind Kind and of type Tp.
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/// The index and subtype parameters are used by the subvector insertion and
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/// extraction shuffle kinds.
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virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp, int Index = 0,
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Type *SubTp = 0) const;
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/// \return The expected cost of cast instructions, such as bitcast, trunc,
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/// zext, etc.
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virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src) const;
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/// \return The expected cost of control-flow related instrutctions such as
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/// Phi, Ret, Br.
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virtual unsigned getCFInstrCost(unsigned Opcode) const;
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/// \returns The expected cost of compare and select instructions.
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virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy = 0) const;
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/// \return The expected cost of vector Insert and Extract.
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/// Use -1 to indicate that there is no information on the index value.
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virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index = -1) const;
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/// \return The cost of Load and Store instructions.
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virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
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unsigned Alignment,
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unsigned AddressSpace) const;
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/// \returns The cost of Intrinsic instructions.
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virtual unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
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ArrayRef<Type *> Tys) const;
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/// \returns The number of pieces into which the provided type must be
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/// split during legalization. Zero is returned when the answer is unknown.
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virtual unsigned getNumberOfParts(Type *Tp) const;
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/// @}
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/// Analysis group identification.
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static char ID;
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};
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/// \brief Create the base case instance of a pass in the TTI analysis group.
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///
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/// This class provides the base case for the stack of TTI analyses. It doesn't
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/// delegate to anything and uses the STTI and VTTI objects passed in to
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/// satisfy the queries.
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ImmutablePass *createNoTargetTransformInfoPass();
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} // End llvm namespace
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#endif
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