llvm-6502/test/CodeGen
Eli Bendersky 50125482d3 This patch teaches x86 fast-isel to generate the native div/idiv instructions
for the sdiv/srem/udiv/urem bitcode instructions.  This is done for the i8,
i16, and i32 types, as well as i64 for the x86_64 target.

Patch by Jim Stichnoth



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179715 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17 20:10:13 +00:00
..
AArch64
ARM Implement ARM unwind opcode assembler. 2013-04-16 12:02:21 +00:00
CPP
Generic
Hexagon
Inputs
MBlaze
Mips [mips] Reapply r179420 and r179421. 2013-04-13 00:55:41 +00:00
MSP430
NVPTX
PowerPC Fix PPC64 CR spill location for callee-saved registers 2013-04-15 02:07:05 +00:00
R600 R600: Make Export Instruction not duplicable 2013-04-17 15:17:39 +00:00
SI
SPARC Add 64-bit multiply and divide instructions for SPARC v9. 2013-04-16 02:57:02 +00:00
Thumb
Thumb2
X86 This patch teaches x86 fast-isel to generate the native div/idiv instructions 2013-04-17 20:10:13 +00:00
XCore [XCore] Extend test to check positve offsets are folded into addresses. 2013-04-16 20:05:52 +00:00