llvm-6502/test/CodeGen
Sanjay Patel 05d5e213c4 merge consecutive stores of extracted vector elements (PR21711)
This is a 2nd try at the same optimization as http://reviews.llvm.org/D6698. 
That patch was checked in at r224611, but reverted at r225031 because it
caused a failure outside of the regression tests.

The cause of the crash was not recognizing consecutive stores that have mixed
source values (loads and vector element extracts), so this patch adds a check
to bail out if any store value is not coming from a vector element extract.

This patch also refactors the shared logic of the constant source and vector
extracted elements source cases into a helper function.

Differential Revision: http://reviews.llvm.org/D6850
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226845 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-22 18:21:26 +00:00
..
AArch64 DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N)) 2015-01-21 23:17:19 +00:00
ARM Fix load-store optimizer on thumbv4t 2015-01-21 22:39:43 +00:00
CPP
Generic
Hexagon [Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns. 2015-01-21 18:13:15 +00:00
Inputs
Mips [mips] Add registers and ALL check prefix to octeon test case. 2015-01-20 16:14:02 +00:00
MSP430
NVPTX
PowerPC [PowerPC] Add r2 as an operand for all calls under both PPC64 ELF V1 and V2 2015-01-19 07:20:27 +00:00
R600 DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N)) 2015-01-21 23:17:19 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86 merge consecutive stores of extracted vector elements (PR21711) 2015-01-22 18:21:26 +00:00
XCore