mirror of
https://github.com/c64scene-ar/llvm-6502.git
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bec5c611e1
Print in decimal for inline immediates, and hex otherwise. Use hex always for offsets in addressing offsets. This approximately matches what the shader compiler does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206335 91177308-0d34-0410-b5e6-96231b3b80d8
420 lines
11 KiB
C++
420 lines
11 KiB
C++
//===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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// \file
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//===----------------------------------------------------------------------===//
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#include "AMDGPUInstPrinter.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
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StringRef Annot) {
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OS.flush();
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printInstruction(MI, OS);
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printAnnotation(OS, Annot);
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}
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void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
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}
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void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
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}
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void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
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}
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void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
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switch (reg) {
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case AMDGPU::VCC:
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O << "vcc";
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return;
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case AMDGPU::SCC:
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O << "scc";
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return;
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case AMDGPU::EXEC:
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O << "exec";
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return;
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case AMDGPU::M0:
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O << "m0";
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return;
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default:
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break;
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}
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char Type;
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unsigned NumRegs;
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if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
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Type = 'v';
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NumRegs = 1;
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} else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
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Type = 's';
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NumRegs = 1;
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} else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
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Type = 'v';
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NumRegs = 2;
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} else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
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Type = 's';
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NumRegs = 2;
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} else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
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Type = 'v';
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NumRegs = 4;
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} else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
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Type = 's';
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NumRegs = 4;
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} else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
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Type = 'v';
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NumRegs = 3;
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} else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
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Type = 'v';
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NumRegs = 8;
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} else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
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Type = 's';
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NumRegs = 8;
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} else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
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Type = 'v';
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NumRegs = 16;
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} else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
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Type = 's';
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NumRegs = 16;
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} else {
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O << getRegisterName(reg);
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return;
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}
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// The low 8 bits encoding value is the register index, for both VGPRs and
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// SGPRs.
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unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
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if (NumRegs == 1) {
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O << Type << RegIdx;
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return;
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}
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O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
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}
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void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
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int32_t SImm = static_cast<int32_t>(Imm);
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if (SImm >= -16 && SImm <= 64) {
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O << SImm;
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return;
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}
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if (Imm == FloatToBits(1.0f) ||
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Imm == FloatToBits(-1.0f) ||
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Imm == FloatToBits(0.5f) ||
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Imm == FloatToBits(-0.5f) ||
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Imm == FloatToBits(2.0f) ||
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Imm == FloatToBits(-2.0f) ||
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Imm == FloatToBits(4.0f) ||
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Imm == FloatToBits(-4.0f)) {
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O << BitsToFloat(Imm);
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return;
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}
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O << formatHex(static_cast<uint64_t>(Imm));
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}
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void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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switch (Op.getReg()) {
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// This is the default predicate state, so we don't need to print it.
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case AMDGPU::PRED_SEL_OFF:
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break;
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default:
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printRegOperand(Op.getReg(), O);
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break;
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}
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} else if (Op.isImm()) {
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printImmediate(Op.getImm(), O);
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} else if (Op.isFPImm()) {
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O << Op.getFPImm();
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} else if (Op.isExpr()) {
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const MCExpr *Exp = Op.getExpr();
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Exp->print(O);
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} else {
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assert(!"unknown operand type in printOperand");
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}
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}
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void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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unsigned Imm = MI->getOperand(OpNum).getImm();
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if (Imm == 2) {
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O << "P0";
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} else if (Imm == 1) {
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O << "P20";
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} else if (Imm == 0) {
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O << "P10";
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} else {
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assert(!"Invalid interpolation parameter slot");
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}
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}
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void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printOperand(MI, OpNo, O);
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O << ", ";
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printOperand(MI, OpNo + 1, O);
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}
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void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, StringRef Asm,
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StringRef Default) {
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const MCOperand &Op = MI->getOperand(OpNo);
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assert(Op.isImm());
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if (Op.getImm() == 1) {
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O << Asm;
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} else {
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O << Default;
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}
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}
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void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "|");
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}
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void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "_SAT");
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}
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void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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union Literal {
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float f;
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int32_t i;
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} L;
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L.i = MI->getOperand(OpNo).getImm();
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O << L.i << "(" << L.f << ")";
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}
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void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
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}
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void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "-");
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}
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void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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switch (MI->getOperand(OpNo).getImm()) {
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default: break;
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case 1:
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O << " * 2.0";
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break;
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case 2:
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O << " * 4.0";
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break;
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case 3:
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O << " / 2.0";
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break;
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}
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}
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void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "+");
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}
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void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "ExecMask,");
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}
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void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "Pred,");
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}
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void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.getImm() == 0) {
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O << " (MASKED)";
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}
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}
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void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const char * chans = "XYZW";
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int sel = MI->getOperand(OpNo).getImm();
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int chan = sel & 3;
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sel >>= 2;
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if (sel >= 512) {
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sel -= 512;
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int cb = sel >> 12;
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sel &= 4095;
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O << cb << "[" << sel << "]";
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} else if (sel >= 448) {
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sel -= 448;
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O << sel;
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} else if (sel >= 0){
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O << sel;
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}
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if (sel >= 0)
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O << "." << chans[chan];
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}
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void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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int BankSwizzle = MI->getOperand(OpNo).getImm();
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switch (BankSwizzle) {
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case 1:
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O << "BS:VEC_021/SCL_122";
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break;
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case 2:
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O << "BS:VEC_120/SCL_212";
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break;
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case 3:
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O << "BS:VEC_102/SCL_221";
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break;
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case 4:
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O << "BS:VEC_201";
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break;
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case 5:
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O << "BS:VEC_210";
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break;
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default:
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break;
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}
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return;
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}
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void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned Sel = MI->getOperand(OpNo).getImm();
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switch (Sel) {
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case 0:
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O << "X";
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break;
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case 1:
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O << "Y";
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break;
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case 2:
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O << "Z";
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break;
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case 3:
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O << "W";
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break;
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case 4:
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O << "0";
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break;
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case 5:
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O << "1";
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break;
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case 7:
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O << "_";
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break;
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default:
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break;
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}
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}
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void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned CT = MI->getOperand(OpNo).getImm();
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switch (CT) {
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case 0:
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O << "U";
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break;
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case 1:
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O << "N";
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break;
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default:
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break;
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}
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}
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void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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int KCacheMode = MI->getOperand(OpNo).getImm();
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if (KCacheMode > 0) {
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int KCacheBank = MI->getOperand(OpNo - 2).getImm();
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O << "CB" << KCacheBank <<":";
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int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
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int LineSize = (KCacheMode == 1)?16:32;
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O << KCacheAddr * 16 << "-" << KCacheAddr * 16 + LineSize;
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}
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}
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void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned SImm16 = MI->getOperand(OpNo).getImm();
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unsigned Msg = SImm16 & 0xF;
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if (Msg == 2 || Msg == 3) {
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unsigned Op = (SImm16 >> 4) & 0xF;
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if (Msg == 3)
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O << "Gs_done(";
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else
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O << "Gs(";
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if (Op == 0) {
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O << "nop";
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} else {
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unsigned Stream = (SImm16 >> 8) & 0x3;
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if (Op == 1)
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O << "cut";
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else if (Op == 2)
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O << "emit";
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else if (Op == 3)
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O << "emit-cut";
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O << " stream " << Stream;
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}
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O << "), [m0] ";
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} else if (Msg == 1)
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O << "interrupt ";
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else if (Msg == 15)
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O << "system ";
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else
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O << "unknown(" << Msg << ") ";
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}
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void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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// Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
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// SIInsertWaits.cpp bits usage does not match ISA docs description but it
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// works so it might be a misprint in docs.
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unsigned SImm16 = MI->getOperand(OpNo).getImm();
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unsigned Vmcnt = SImm16 & 0xF;
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unsigned Expcnt = (SImm16 >> 4) & 0xF;
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unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
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if (Vmcnt != 0xF)
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O << "vmcnt(" << Vmcnt << ") ";
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if (Expcnt != 0x7)
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O << "expcnt(" << Expcnt << ") ";
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if (Lgkmcnt != 0x7)
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O << "lgkmcnt(" << Lgkmcnt << ")";
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}
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#include "AMDGPUGenAsmWriter.inc"
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