llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-19 01:13:25 +00:00

History

Dan Gohman 8be6bbe5bf Eliminate the ISel priority queue, which used the topological order for a priority function. Instead, just iterate over the AllNodes list, which is already in topological order. This eliminates a fair amount of bookkeeping, and speeds up the isel phase by about 15% on many testcases. The impact on most targets is that AddToISelQueue calls can be simply removed. In the x86 target, there are two additional notable changes. The rule-bending AND+SHIFT optimization in MatchAddress that creates new pre-isel nodes during isel is now a little more verbose, but more robust. Instead of either creating an invalid DAG or creating an invalid topological sort, as it has historically done, it can now just insert the new nodes into the node list at a position where they will be consistent with the topological ordering. Also, the address-matching code has logic that checked to see if a node was "already selected". However, when a node is selected, it has all its uses taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any further visits from MatchAddress. This code is now removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8		2008-11-05 04:14:16 +00:00
..
CMakeLists.txt
DelaySlotFiller.cpp
FPMover.cpp
Makefile
README.txt
Sparc.h
Sparc.td
SparcAsmPrinter.cpp
SparcCallingConv.td
SparcInstrFormats.td
SparcInstrInfo.cpp	Const-ify several TargetInstrInfo methods.	2008-10-16 01:49:15 +00:00
SparcInstrInfo.h	Const-ify several TargetInstrInfo methods.	2008-10-16 01:49:15 +00:00
SparcInstrInfo.td
SparcISelDAGToDAG.cpp	Eliminate the ISel priority queue, which used the topological order for a	2008-11-05 04:14:16 +00:00
SparcISelLowering.cpp	Teach DAGCombine to fold constant offsets into GlobalAddress nodes,	2008-10-18 02:06:02 +00:00
SparcISelLowering.h	Teach DAGCombine to fold constant offsets into GlobalAddress nodes,	2008-10-18 02:06:02 +00:00
SparcRegisterInfo.cpp
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetAsmInfo.cpp
SparcTargetAsmInfo.h
SparcTargetMachine.cpp	Fix command-line option printing to print two spaces where needed,	2008-10-14 20:25:08 +00:00
SparcTargetMachine.h

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots