Renato Golin 06b11e36e5 Do not emit intermediate register for zero FP immediate ... This updates check for double precision zero floating point constant to allow use of instruction with immediate value rather than temporary register. Currently "a == 0.0", where "a" is of "double" type generates: vmov.i32 d16, #0x0 vcmpe.f64 d0, d16 With this change it becomes: vcmpe.f64 d0, #0 Patch by Sergey Dmitrouk. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220486 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-23 15:31:50 +00:00
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AArch64	[AArch64] Cleanup A57PBQPConstraints	2014-10-22 12:40:20 +00:00
ARM	Do not emit intermediate register for zero FP immediate	2014-10-23 15:31:50 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC	[PATCH] Support select-cc for VSFRC when VSX is enabled	2014-10-22 16:58:20 +00:00
R600	R600/SI: Add another failing testcase for i1 copies	2014-10-22 05:30:42 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	Add minnum / maxnum codegen	2014-10-21 23:01:01 +00:00
XCore