llvm-6502/lib/Target/Alpha
2010-10-29 17:29:13 +00:00
..
AsmPrinter
TargetInfo
Alpha.h
Alpha.td
AlphaBranchSelector.cpp
AlphaCallingConv.td
AlphaCodeEmitter.cpp Make <target>CodeEmitter::getBinaryCodeForInstr() a const method. 2010-10-08 00:21:28 +00:00
AlphaInstrFormats.td
AlphaInstrInfo.cpp
AlphaInstrInfo.h
AlphaInstrInfo.td
AlphaISelDAGToDAG.cpp
AlphaISelLowering.cpp Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 2010-10-29 17:29:13 +00:00
AlphaISelLowering.h Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 2010-10-29 17:29:13 +00:00
AlphaJITInfo.cpp
AlphaJITInfo.h
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaMCAsmInfo.cpp
AlphaMCAsmInfo.h
AlphaRegisterInfo.cpp
AlphaRegisterInfo.h
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td Add support to model pipeline bypass / forwarding. 2010-09-28 23:50:49 +00:00
AlphaSelectionDAGInfo.cpp
AlphaSelectionDAGInfo.h
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetMachine.cpp
AlphaTargetMachine.h
CMakeLists.txt Removed a bunch of unnecessary target_link_libraries. 2010-09-28 22:39:14 +00:00
Makefile
README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html