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llvm-6502/test/CodeGen/R600
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Vincent Lejeune df98ad3959 R600: Lower int_load_input to copyFromReg instead of Register node 
It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:51:06 +00:00
..
128bit-kernel-args.ll
add.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
alu-split.ll R600: use native for alu 2013-04-30 00:14:38 +00:00
and.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
bfe_uint.ll R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns 2013-05-10 02:09:45 +00:00
bfi_int.ll R600: Use depth first scheduling algorithm 2013-05-17 16:50:44 +00:00
call_fs.ll R600: Stop emitting the instruction type byte before each instruction 2013-05-06 17:50:44 +00:00
cf_end.ll R600: Stop emitting the instruction type byte before each instruction 2013-05-06 17:50:44 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
disconnected-predset-break-bug.ll R600: use native for alu 2013-04-30 00:14:38 +00:00
elf.ll R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE 2013-04-26 18:32:24 +00:00
elf.r600.ll R600: Emit config values in register / value pairs 2013-05-06 17:50:51 +00:00
fabs.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fadd.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fcmp-cnd.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
fcmp-cnde-int-args.ll
fcmp.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
fdiv.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
floor.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fmad.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fmax.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fmin.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fmul.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fmul.v4f32.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
fp_to_sint.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
fp_to_uint.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
fsub.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
i8-to-double-to-float.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
icmp-select-sete-reverse-args.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
imm.ll
jump-address.ll
kcache-fold.ll
legalizedag-bug-expand-setcc.ll
lit.local.cfg
literals.ll R600: Signed literals are 64bits wide 2013-05-02 21:53:03 +00:00
llvm.AMDGPU.imax.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.imin.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.mul.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
llvm.AMDGPU.tex.ll R600: Improve texture handling 2013-05-17 16:50:20 +00:00
llvm.AMDGPU.trunc.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.umax.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.umin.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.cos.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
llvm.pow.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
llvm.SI.fs.interp.constant.ll
llvm.SI.imageload.ll R600/SI: Add lit tests for llvm.SI.imageload and llvm.SI.resinfo intrinsics 2013-05-08 13:07:29 +00:00
llvm.SI.resinfo.ll R600/SI: Add lit tests for llvm.SI.imageload and llvm.SI.resinfo intrinsics 2013-05-08 13:07:29 +00:00
llvm.SI.sample.ll
llvm.sin.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
load-input-fold.ll R600: Lower int_load_input to copyFromReg instead of Register node 2013-05-17 16:51:06 +00:00
load.ll
loop-address.ll TBAA: remove !tbaa from testing cases if not used. 2013-04-30 17:52:57 +00:00
lshl.ll
lshr.ll
mul.ll R600: Expand MUL for v4i32/v2i32 2013-05-10 02:09:34 +00:00
mulhu.ll
or.ll R600: Expand vector or, shl, srl, and xor nodes 2013-05-03 17:21:31 +00:00
predicates.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
pv.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
r600-encoding.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
README
reciprocal.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-if-2.ll
schedule-if.ll
schedule-vs-if-nested-loop.ll
sdiv.ll
selectcc-cnd.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
selectcc-cnde-int.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
selectcc-icmp-select-float.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
selectcc-opt.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
set-dx10.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
setcc.ll
seto.ll
setuo.ll
shl.ll R600: Expand vector or, shl, srl, and xor nodes 2013-05-03 17:21:31 +00:00
short-args.ll
sint_to_fp.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
sra.ll R600: Expand SRA for v4i32/v2i32 2013-05-10 02:09:29 +00:00
srl.ll R600: Expand vector or, shl, srl, and xor nodes 2013-05-03 17:21:31 +00:00
store.ll
store.r600.ll
sub.ll R600: Expand SUB for v2i32/v4i32 2013-05-10 02:09:39 +00:00
udiv.ll
uint_to_fp.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
uitofp.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
unsupported-cc.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
urecip.ll
urem.ll
vselect.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
xor.ll R600: Expand vector or, shl, srl, and xor nodes 2013-05-03 17:21:31 +00:00

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.