llvm-6502/lib/Target/Sparc
Rafael Espindola 9472fd7403 Refactor the setting of PrivateGlobalPrefix.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 23:39:26 +00:00
..
MCTargetDesc Refactor the setting of PrivateGlobalPrefix. 2013-12-02 23:39:26 +00:00
TargetInfo [CMake] Let add_public_tablegen_target responsible to provide dependency to CommonTableGen. 2013-11-28 17:04:04 +00:00
CMakeLists.txt [CMake] Let add_public_tablegen_target() provide intrinsics_gen, too. 2013-11-28 17:04:31 +00:00
DelaySlotFiller.cpp
LLVMBuild.txt
Makefile
README.txt
Sparc.h [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64. 2013-11-24 20:23:25 +00:00
Sparc.td Change the default of AsmWriterClassName and isMCAsmWriter. 2013-12-02 04:55:42 +00:00
SparcAsmPrinter.cpp [SparcV9]: Do not emit .register directives for global registers that are clobbered by calls but not used in the function itself. 2013-11-24 18:41:49 +00:00
SparcCallingConv.td
SparcCodeEmitter.cpp
SparcFrameLowering.cpp SparcFrameLowering.cpp: Prune 'DL' [-Wunused-variable] 2013-11-25 00:52:46 +00:00
SparcFrameLowering.h [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64. 2013-11-24 20:23:25 +00:00
SparcInstr64Bit.td [Sparc]: Implement LEA pattern for sparcv9. 2013-11-24 20:07:35 +00:00
SparcInstrFormats.td
SparcInstrInfo.cpp [weak vtables] Remove a bunch of weak vtables 2013-11-19 00:57:56 +00:00
SparcInstrInfo.h [weak vtables] Remove a bunch of weak vtables 2013-11-19 00:57:56 +00:00
SparcInstrInfo.td [Sparc]: Implement LEA pattern for sparcv9. 2013-11-24 20:07:35 +00:00
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp [SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64. 2013-11-24 17:41:41 +00:00
SparcISelLowering.h [SparcV9] Handle i64 <-> float conversions in sparcv9 mode. 2013-11-03 12:28:40 +00:00
SparcJITInfo.cpp
SparcJITInfo.h
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcRegisterInfo.cpp [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64. 2013-11-24 20:23:25 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcRelocations.h
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetMachine.cpp
SparcTargetMachine.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Implement JIT support

* Use %g0 directly to materialize 0. No instruction is required.