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https://github.com/c64scene-ar/llvm-6502.git
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dafa504341
* Added some Format 4 classes, but not instructions * Added notes on missing sections with FIXMEs * Added RDCCR instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6388 91177308-0d34-0410-b5e6-96231b3b80d8
65 lines
1.6 KiB
C++
65 lines
1.6 KiB
C++
//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
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// vim:ft=cpp
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Format #2 classes
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//
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class F2 : InstV9 { // Format 2 instructions
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bits<3> op2;
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set op = 0; // Op = 0
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set Inst{24-22} = op2;
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}
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// Format 2.1 instructions
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class F2_1<string name> : F2 {
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bits<5> rd;
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bits<22> imm;
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set Name = name;
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set Inst{29-25} = rd;
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set Inst{21-0} = imm;
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}
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class F2_br : F2 { // Format 2 Branch instruction
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bit annul; // All branches have an annul bit
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set Inst{29} = annul;
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set isBranch = 1; // All instances are branch instructions
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}
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class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
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bits<22> disp;
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set Name = name;
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set Inst{28-25} = cond;
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set Inst{21-0} = disp;
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}
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class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
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bits<2> cc;
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bits<19> disp;
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bit predict;
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set Name = name;
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set Inst{28-25} = cond;
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set Inst{21-20} = cc;
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set Inst{19} = predict;
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set Inst{18-0} = disp;
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}
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class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
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// Variables exposed by the instruction...
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bit predict;
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bits<5> rs1;
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bits<16> disp;
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set Name = name;
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set Inst{28} = 0;
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set Inst{27-25} = rcond;
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// Inst{24-22} = op2 field
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set Inst{21-20} = disp{15-14};
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set Inst{19} = predict;
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set Inst{18-14} = rs1;
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set Inst{13-0 } = disp{13-0};
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}
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