Tim Northover 09bec94c16 ARM: add test for crc32 instructions in CodeGen. ... Somehow we seem to have ended up without any actual tests of the CodeGen side. Easy enough to fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225930 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-14 01:43:33 +00:00
..
AArch64	Fix PR22179.	2015-01-10 23:41:24 +00:00
ARM	ARM: add test for crc32 instructions in CodeGen.	2015-01-14 01:43:33 +00:00
CPP
Generic	CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.	2014-12-19 20:50:07 +00:00
Hexagon	[Hexagon] Adding dealloc_return encoding and absolute address stores.	2015-01-06 16:15:15 +00:00
Inputs	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Mips	Insert random noops to increase security against ROP attacks (llvm)	2015-01-14 01:07:26 +00:00
MSP430
NVPTX	[NVPTX] Fix bugs related to isSingleValueType	2014-12-17 17:59:04 +00:00
PowerPC	[PowerPC] Fix the noop-insert test	2015-01-14 01:37:21 +00:00
R600	R600/SI: Remove some redudant load testcases.	2015-01-14 01:35:26 +00:00
SPARC	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
SystemZ	Use the integrated assembler as default on SystemZ	2015-01-13 19:45:16 +00:00
Thumb	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb2	[ARM] Fix a bug in constant island pass that was triggering an assertion.	2015-01-08 20:44:50 +00:00
X86	Insert random noops to increase security against ROP attacks (llvm)	2015-01-14 01:07:26 +00:00
XCore	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00