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Currently when DAGCombine converts loads feeding a switch into a switch of addresses feeding a load the new load inherits the isInvariant flag of the left side. This is incorrect since invariant loads can be reordered in cases where it is illegal to reoarder normal loads. This patch adds an isInvariant parameter to getExtLoad() and updates all call sites to pass in the data if they have it or false if they don't. It also changes the DAGCombine to use that data to make the right decision when creating the new load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214449 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
Disassembler | ||
InstPrinter | ||
MCTargetDesc | ||
TargetInfo | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
Makefile | ||
README.txt | ||
XCore.h | ||
XCore.td | ||
XCoreAsmPrinter.cpp | ||
XCoreCallingConv.td | ||
XCoreFrameLowering.cpp | ||
XCoreFrameLowering.h | ||
XCoreFrameToArgsOffsetElim.cpp | ||
XCoreInstrFormats.td | ||
XCoreInstrInfo.cpp | ||
XCoreInstrInfo.h | ||
XCoreInstrInfo.td | ||
XCoreISelDAGToDAG.cpp | ||
XCoreISelLowering.cpp | ||
XCoreISelLowering.h | ||
XCoreLowerThreadLocal.cpp | ||
XCoreMachineFunctionInfo.cpp | ||
XCoreMachineFunctionInfo.h | ||
XCoreMCInstLower.cpp | ||
XCoreMCInstLower.h | ||
XCoreRegisterInfo.cpp | ||
XCoreRegisterInfo.h | ||
XCoreRegisterInfo.td | ||
XCoreSelectionDAGInfo.cpp | ||
XCoreSelectionDAGInfo.h | ||
XCoreSubtarget.cpp | ||
XCoreSubtarget.h | ||
XCoreTargetMachine.cpp | ||
XCoreTargetMachine.h | ||
XCoreTargetObjectFile.cpp | ||
XCoreTargetObjectFile.h | ||
XCoreTargetStreamer.h | ||
XCoreTargetTransformInfo.cpp |
To-do ----- * Instruction encodings * Tailcalls * Investigate loop alignment * Add builtins