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0ee5398b7f
Summary: MIPS32r6/MIPS64r6 support has not been added yet. inlineasm-cnstrnt-reg.ll: Explicitly specify the CPU since it will not work on MIPS32r6/MIPS64r6 when -integrated-as is the default. We can't change the mnemonic since the LO register is an implicit def of mtlo and MIPS32r6/MIPS64r6 has no instructions that use LO. 2008-08-01-AsmInline.ll: Explicitly specify the CPU since MIPS32r6/MIPS64r6 will correctly emit different code and this is a regression test. mips64instrs.ll and mips64muldiv.ll Check registers and the way the multiply is used in m1 divrem.ll Check registers and use multiple filecheck prefixes to limit redundancy Reviewers: vmedic, jkolek, zoran.jovanovic, matheusalmeida Reviewed By: matheusalmeida Subscribers: matheusalmeida Differential Revision: http://reviews.llvm.org/D3894 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210656 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.4 KiB
LLVM
46 lines
1.4 KiB
LLVM
; Positive test for inline register constraints
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;
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; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
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define i32 @main() nounwind {
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entry:
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; r with char
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;CHECK: #APP
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;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},23
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;CHECK: #NO_APP
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tail call i8 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i8 27, i8 23) nounwind
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; r with short
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;CHECK: #APP
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;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},13
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;CHECK: #NO_APP
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tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i16 17, i16 13) nounwind
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; r with int
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;CHECK: #APP
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;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3
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;CHECK: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind
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; Now c with 1024: make sure register $25 is picked
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; CHECK: #APP
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; CHECK: addiu $25,${{[0-9]+}},1024
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; CHECK: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind
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; Now l with 1024: make sure register lo is picked. We do this by checking the instruction
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; after the inline expression for a mflo to pull the value out of lo.
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; CHECK: #APP
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; CHECK-NEXT: mtlo ${{[0-9]+}}
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; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}}
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: mflo ${{[0-9]+}}
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%bosco = alloca i32, align 4
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call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
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store volatile i32 %4, i32* %bosco, align 4
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ret i32 0
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}
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