mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
9d2fa87816
compiled on mips32r1 processors because it uses synci and rdhwr instructions which are supported only on mips32r2, so I replaced this function with the call to function cacheflush which works for both mips32r1 and mips32r2. Patch by Sasa Stankovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141564 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
2.4 KiB
C++
81 lines
2.4 KiB
C++
//===- Memory.cpp - Memory Handling Support ---------------------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file defines some helpful functions for allocating memory and dealing
|
|
// with memory mapped files
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/Support/Memory.h"
|
|
#include "llvm/Support/Valgrind.h"
|
|
#include "llvm/Config/config.h"
|
|
|
|
#if defined(__mips__)
|
|
#include <sys/cachectl.h>
|
|
#endif
|
|
|
|
namespace llvm {
|
|
using namespace sys;
|
|
}
|
|
|
|
// Include the platform-specific parts of this class.
|
|
#ifdef LLVM_ON_UNIX
|
|
#include "Unix/Memory.inc"
|
|
#endif
|
|
#ifdef LLVM_ON_WIN32
|
|
#include "Windows/Memory.inc"
|
|
#endif
|
|
|
|
extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
|
|
|
|
/// InvalidateInstructionCache - Before the JIT can run a block of code
|
|
/// that has been emitted it must invalidate the instruction cache on some
|
|
/// platforms.
|
|
void llvm::sys::Memory::InvalidateInstructionCache(const void *Addr,
|
|
size_t Len) {
|
|
|
|
// icache invalidation for PPC and ARM.
|
|
#if defined(__APPLE__)
|
|
|
|
# if (defined(__POWERPC__) || defined (__ppc__) || \
|
|
defined(_POWER) || defined(_ARCH_PPC)) || defined(__arm__)
|
|
sys_icache_invalidate(Addr, Len);
|
|
# endif
|
|
|
|
#else
|
|
|
|
# if (defined(__POWERPC__) || defined (__ppc__) || \
|
|
defined(_POWER) || defined(_ARCH_PPC)) && defined(__GNUC__)
|
|
const size_t LineSize = 32;
|
|
|
|
const intptr_t Mask = ~(LineSize - 1);
|
|
const intptr_t StartLine = ((intptr_t) Addr) & Mask;
|
|
const intptr_t EndLine = ((intptr_t) Addr + Len + LineSize - 1) & Mask;
|
|
|
|
for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
|
|
asm volatile("dcbf 0, %0" : : "r"(Line));
|
|
asm volatile("sync");
|
|
|
|
for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
|
|
asm volatile("icbi 0, %0" : : "r"(Line));
|
|
asm volatile("isync");
|
|
# elif defined(__arm__) && defined(__GNUC__)
|
|
// FIXME: Can we safely always call this for __GNUC__ everywhere?
|
|
char *Start = (char*) Addr;
|
|
char *End = Start + Len;
|
|
__clear_cache(Start, End);
|
|
# elif defined(__mips__)
|
|
cacheflush((char*)Addr, Len, BCACHE);
|
|
# endif
|
|
|
|
#endif // end apple
|
|
|
|
ValgrindDiscardTranslations(Addr, Len);
|
|
}
|