Tim Northover 530869f8bc AArch64: simplify tbl/tbx polymorphism ... The table argument is always 128-bit (and interpreted as <16 x i8>) so the extra specifier for it is just clutter. No user-visible behaviour change, so no tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202258 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-26 11:55:09 +00:00
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AArch64	AArch64: simplify tbl/tbx polymorphism	2014-02-26 11:55:09 +00:00
ARM	Stop test/CodeGen/ARM/a15.ll targetting non-ARM targets.	2014-02-26 11:26:18 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC	Account for 128-bit integer operations in PPCCTRLoops	2014-02-25 20:51:50 +00:00
R600	R600/SI: Custom select 64-bit ADD	2014-02-25 21:36:18 +00:00
SPARC	SPARC: Implement TRAP lowering. Matches what GCC emits.	2014-02-23 21:43:52 +00:00
SystemZ
Thumb
Thumb2	ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block	2014-02-26 11:27:28 +00:00
X86	Store a DataLayout in Module.	2014-02-25 20:01:08 +00:00
XCore	[XCore] Add intrinsic for CLRPT (clear port time) instruction.	2014-02-25 17:31:15 +00:00