llvm-6502/lib/CodeGen
2010-10-30 01:26:19 +00:00
..
AsmPrinter Ignore empty blocks. 2010-10-28 22:11:59 +00:00
SelectionDAG Remove DAG combiner patch to fold vector splats. Instcombiner does it now. 2010-10-29 22:03:02 +00:00
AggressiveAntiDepBreaker.cpp
AggressiveAntiDepBreaker.h
Analysis.cpp Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 2010-10-29 17:29:13 +00:00
AntiDepBreaker.h
BranchFolding.cpp
BranchFolding.h
CalcSpillWeights.cpp Begin adding static dependence information to passes, which will allow us to 2010-10-12 19:48:12 +00:00
CallingConvLower.cpp
CMakeLists.txt This is a prototype of an experimental register allocation 2010-10-22 23:09:15 +00:00
CodeGen.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp Fix a miscompile in 186.crafty for Thumb2 that was exposed by Evan's 2010-10-02 01:49:29 +00:00
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
DwarfEHPrepare.cpp This may be an ARM target, so check for _Unwind_SjLj_Resume. 2010-10-29 07:46:01 +00:00
ELF.h
ELFCodeEmitter.cpp
ELFCodeEmitter.h
ELFWriter.cpp
ELFWriter.h
GCMetadata.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
IfConversion.cpp When the "true" and "false" blocks of a diamond if-conversion are the same, 2010-10-26 00:02:24 +00:00
InlineSpiller.cpp Print out register class of spilled register. 2010-10-30 01:26:09 +00:00
IntrinsicLowering.cpp Get rid of pop_macro warnings on MSVC. 2010-09-24 19:48:47 +00:00
LatencyPriorityQueue.cpp
LiveInterval.cpp Teach ConnectedVNInfoEqClasses::Classify to deal with unused values. 2010-10-29 17:37:29 +00:00
LiveIntervalAnalysis.cpp Teach MachineBasicBlock::print() to annotate instructions and blocks with 2010-10-26 20:21:46 +00:00
LiveIntervalUnion.cpp Remove the vector of live vregs. I thought we would need to track 2010-10-26 22:58:24 +00:00
LiveIntervalUnion.h Remove the vector of live vregs. I thought we would need to track 2010-10-26 22:58:24 +00:00
LiveRangeEdit.cpp Remember to keep track of rematted values. 2010-10-20 22:50:42 +00:00
LiveRangeEdit.h Fix sign error. 2010-10-29 18:21:18 +00:00
LiveStackAnalysis.cpp Make the spiller responsible for updating the LiveStacks analysis. 2010-10-26 00:11:33 +00:00
LiveVariables.cpp Begin adding static dependence information to passes, which will allow us to 2010-10-12 19:48:12 +00:00
LLVMTargetMachine.cpp Add TypeBasedAliasAnalysis to the standard pass lists. Note that it 2010-10-18 18:50:27 +00:00
LocalStackSlotAllocation.cpp
LowerSubregs.cpp
MachineBasicBlock.cpp Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is needed 2010-10-30 01:26:14 +00:00
MachineCSE.cpp Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857. 2010-10-29 23:36:03 +00:00
MachineDominators.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
MachineFunction.cpp Include MachineBasicBlock numbers in viewCFG() output. 2010-10-30 01:26:19 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Unbreak build. 2010-10-22 21:49:09 +00:00
MachineLICM.cpp Use instruction itinerary to determine what instructions are 'cheap'. 2010-10-26 02:08:50 +00:00
MachineLoopInfo.cpp Begin adding static dependence information to passes, which will allow us to 2010-10-12 19:48:12 +00:00
MachineModuleInfo.cpp CodeGen-Windows: Only emit _fltused if a VarArg function is called with floating point args. 2010-10-21 00:08:21 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE. 2010-10-06 23:54:39 +00:00
MachineSink.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
MachineSSAUpdater.cpp
MachineVerifier.cpp Disable more of physical register live intervals verification. 2010-10-30 01:26:11 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizePHIs.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
Passes.cpp
PeepholeOptimizer.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
PHIElimination.cpp Now with fewer extraneous semicolons! 2010-10-07 22:25:06 +00:00
PHIElimination.h Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
PostRAHazardRecognizer.cpp
PostRASchedulerList.cpp
PreAllocSplitting.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
ProcessImplicitDefs.cpp Begin adding static dependence information to passes, which will allow us to 2010-10-12 19:48:12 +00:00
PrologEpilogInserter.cpp Formatting. 2010-10-27 16:30:18 +00:00
PrologEpilogInserter.h Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
PseudoSourceValue.cpp
README.txt
RegAllocBase.h Jakob's review of the basic register allocator. 2010-10-26 18:34:01 +00:00
RegAllocBasic.cpp Jakob's review of the basic register allocator. 2010-10-26 18:34:01 +00:00
RegAllocFast.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
RegAllocLinearScan.cpp Make MachineDominators available for SplitEditor. We are going to need it for 2010-10-28 20:34:50 +00:00
RegAllocPBQP.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
RegisterCoalescer.cpp Analysis groups need to initialize their default implementations. 2010-10-13 21:49:58 +00:00
RegisterScavenging.cpp
RenderMachineFunction.cpp The variable liTRC is not used for anything useful, zap it 2010-10-21 16:04:43 +00:00
RenderMachineFunction.h Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
ScheduleDAG.cpp
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp Putting r117193 back except for the compile time cost. Rather than assuming fallthroughs uses all registers, just gather the union of all successor liveins. 2010-10-27 23:17:17 +00:00
ScheduleDAGInstrs.h Properly model the latency of register defs which are 1) function returns or 2010-10-23 02:10:46 +00:00
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp
ShrinkWrapping.cpp
SimpleRegisterCoalescing.cpp Unbreak build. 2010-10-22 21:49:09 +00:00
SimpleRegisterCoalescing.h Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
SjLjEHPrepare.cpp Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any 2010-10-19 23:27:08 +00:00
SlotIndexes.cpp Now with fewer extraneous semicolons! 2010-10-07 22:25:06 +00:00
Spiller.cpp Make the spiller responsible for updating the LiveStacks analysis. 2010-10-26 00:11:33 +00:00
Spiller.h In which I learn how to forward declare template classes. 2010-10-25 17:27:30 +00:00
SplitKit.cpp Make sure copies are inserted after any exception handling labels at the top of 2010-10-30 01:26:16 +00:00
SplitKit.h Replace SplitKit SSA update with an iterative algorithm very similar to the one 2010-10-28 20:34:52 +00:00
Splitter.cpp Begin adding static dependence information to passes, which will allow us to 2010-10-12 19:48:12 +00:00
Splitter.h Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
StackProtector.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
StackSlotColoring.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
StrongPHIElimination.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
TailDuplication.cpp
TargetInstrInfoImpl.cpp
TargetLoweringObjectFileImpl.cpp COFF: Add IMAGE_SCN_MEM_READ to text sections. 2010-10-27 18:52:29 +00:00
TwoAddressInstructionPass.cpp Remove some variables that are never really used 2010-10-21 16:03:28 +00:00
UnreachableBlockElim.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
VirtRegMap.cpp Now with fewer extraneous semicolons! 2010-10-07 22:25:06 +00:00
VirtRegMap.h
VirtRegRewriter.cpp Properly handle reloading and spilling around partial redefines in 2010-10-11 18:10:36 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.