Matt Arsenault 0b87955888 R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec* ... There is not such thing as a 0-data ds instruction, and the data operand needs to be a vgpr set to something meaningful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210756 91177308-0d34-0410-b5e6-96231b3b80d8		2014-06-12 08:21:54 +00:00
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AArch64	[AArch64] Basic Sched Model for Cortex-A57.	2014-06-11 21:06:56 +00:00
ARM	Global merge for global symbols.	2014-06-11 06:44:53 +00:00
CPP	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Generic
Hexagon	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Inputs
Mips	[mips][mips64r6] Improve tests affected by the changes to multiplies and divides	2014-06-11 15:48:00 +00:00
MSP430	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
NVPTX	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
PowerPC	[PPC64LE] Recognize shufflevector patterns for little endian	2014-06-10 14:35:01 +00:00
R600	R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*	2014-06-12 08:21:54 +00:00
SPARC	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Thumb	Fix a bug in the Thumb1 ARM Load/Store optimizer	2014-06-10 16:39:21 +00:00
Thumb2	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
X86	[FastISel][x86] Add testcase for r210719.	2014-06-12 03:54:05 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00