llvm-6502/lib/Target/Sparc
2013-09-22 09:54:42 +00:00
..
MCTargetDesc [Sparc] Add support for TLS in sparc. 2013-09-22 06:48:52 +00:00
TargetInfo
CMakeLists.txt [Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter. 2013-09-22 09:54:42 +00:00
DelaySlotFiller.cpp
LLVMBuild.txt
Makefile [Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter. 2013-09-22 09:54:42 +00:00
README.txt
Sparc.h
Sparc.td [Sparc] Add long double (f128) instructions to sparc backend. 2013-08-25 18:30:06 +00:00
SparcAsmPrinter.cpp [Sparc] Add support for TLS in sparc. 2013-09-22 06:48:52 +00:00
SparcCallingConv.td [Sparc] Correctly handle call to functions with ReturnsTwice attribute. 2013-09-05 05:32:16 +00:00
SparcFrameLowering.cpp
SparcFrameLowering.h
SparcInstr64Bit.td [Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended. 2013-09-22 08:51:55 +00:00
SparcInstrFormats.td [Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter. 2013-09-22 09:54:42 +00:00
SparcInstrInfo.cpp [Sparc] Implement spill and load for long double(f128) registers. 2013-09-02 18:32:45 +00:00
SparcInstrInfo.h
SparcInstrInfo.td [Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter. 2013-09-22 09:54:42 +00:00
SparcISelDAGToDAG.cpp ISelDAG: spot chain cycles involving MachineNodes 2013-09-22 08:21:56 +00:00
SparcISelLowering.cpp [Sparc] Add support for TLS in sparc. 2013-09-22 06:48:52 +00:00
SparcISelLowering.h [Sparc] Add support for TLS in sparc. 2013-09-22 06:48:52 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcRegisterInfo.cpp [Sparc] Correctly handle call to functions with ReturnsTwice attribute. 2013-09-05 05:32:16 +00:00
SparcRegisterInfo.h [Sparc] Correctly handle call to functions with ReturnsTwice attribute. 2013-09-05 05:32:16 +00:00
SparcRegisterInfo.td
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp [Sparc] Add long double (f128) instructions to sparc backend. 2013-08-25 18:30:06 +00:00
SparcSubtarget.h [Sparc] Add long double (f128) instructions to sparc backend. 2013-08-25 18:30:06 +00:00
SparcTargetMachine.cpp
SparcTargetMachine.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Implement JIT support

* Use %g0 directly to materialize 0. No instruction is required.