Bill Schmidt 0d6423b476 Use new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.ll ... While testing some experimental code to add vector-scalar registers to PowerPC, I noticed that a couple of independent instructions were flipped by the scheduler. The new CHECK-DAG support is perfect for avoiding this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182020 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-16 16:15:18 +00:00
..
AArch64	Add more test coverage for addFrameMove.	2013-05-16 15:18:50 +00:00
ARM	ARM ISel: Don't create illegal types during LowerMUL	2013-05-14 22:33:24 +00:00
CPP
Generic	TBAA: remove !tbaa from testing cases if not used.	2013-04-30 17:52:57 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips	Add more addFrameMove test coverage.	2013-05-16 14:51:26 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX
PowerPC	Use new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.ll	2013-05-16 16:15:18 +00:00
R600	R600/SI: Add lit test coverage for the remaining patterns added recently	2013-05-14 09:53:30 +00:00
SI
SPARC	Recognize sparc64 as an alias for sparcv9 triples.	2013-05-14 17:47:27 +00:00
SystemZ	[SystemZ] Make use of SUBTRACT HALFWORD	2013-05-15 15:05:29 +00:00
Thumb	LocalStackSlotAllocation improvements	2013-04-30 20:04:37 +00:00
Thumb2	Fix ARM FastISel tests, as a first step to enabling ARM FastISel	2013-05-14 16:26:38 +00:00
X86	Add more addFrameMove test coverage.	2013-05-16 16:09:54 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00