James Y Knight 0e13ba8208 Sparc: Prefer reg+reg address encoding when only one register used. ... Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces. Futhermore, reg+imm is invalid for the (not yet supported) "alternate address space" instructions. Differential Revision: http://reviews.llvm.org/D8753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236107 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-29 14:54:44 +00:00
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AArch64	[AArch64] LORID_EL1 register must be treated as read-only	2015-04-20 16:54:37 +00:00
ARM	[ARM] Add v8.1a "Privileged Access Never" extension	2015-04-16 11:34:25 +00:00
Hexagon
Mips	[mips][microMIPSr6] Implement CACHE and PREF instructions	2015-04-21 11:17:25 +00:00
PowerPC	[PowerPC] Use sync inst alias when printing	2015-04-23 23:05:08 +00:00
Sparc	Sparc: Prefer reg+reg address encoding when only one register used.	2015-04-29 14:54:44 +00:00
SystemZ	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
X86
XCore