Matt Arsenault 0e1619e77c R600: Fix mishandling of load / store chains. ... Fixes various bugs with reordering loads and stores. Scalarized vector loads weren't collecting the chains at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212473 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-07 18:34:45 +00:00
..
AArch64	CodeGen: it turns out that NAND is not the same thing as BIC. At all.	2014-07-07 09:06:35 +00:00
ARM	ARM: properly lower dllimport'ed global values	2014-07-07 05:18:35 +00:00
CPP	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Generic	Add a new attribute called 'jumptable' that creates jump-instruction tables for functions marked with this attribute.	2014-06-05 19:29:43 +00:00
Hexagon	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Inputs
Mips	[mips] Add tests for the 'ret', 'call', and 'indirectbr' LLVM IR instruction.	2014-07-04 15:16:14 +00:00
MSP430	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
NVPTX	[NVPTX] Add reflect intrinsic (better than matching by function name)	2014-06-27 18:36:11 +00:00
PowerPC	llvm-readobj: fix MachO relocatoin printing a bit.	2014-07-04 10:57:56 +00:00
R600	R600: Fix mishandling of load / store chains.	2014-07-07 18:34:45 +00:00
SPARC	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
SystemZ	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Thumb	ARM: Fix fastcc calling convention for Thumb1	2014-06-13 08:33:03 +00:00
Thumb2	ARM: Fix TPsoft for Thumb mode	2014-06-24 15:45:59 +00:00
X86	[x86] Teach the new vector shuffle lowering code to handle what is	2014-07-07 09:06:58 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00