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https://github.com/c64scene-ar/llvm-6502.git
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debf7d345a
When doing a partword atomic operation, a lwarx was being paired with a stdcx. instead of a stwcx. when compiling for a 64-bit target. The target has nothing to do with it in this case; we always need a stwcx. Thanks to Kai Nacke for reporting the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178559 91177308-0d34-0410-b5e6-96231b3b80d8
17 lines
583 B
LLVM
17 lines
583 B
LLVM
; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define weak_odr void @_D4core6atomic49__T11atomicStoreVE4core6atomic11MemoryOrder3ThThZ11atomicStoreFNaNbKOhhZv(i8* %val_arg, i8 zeroext %newval_arg) {
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entry:
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%newval = alloca i8
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%ordering = alloca i32, align 4
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store i8 %newval_arg, i8* %newval
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%tmp = load i8* %newval
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store atomic volatile i8 %tmp, i8* %val_arg seq_cst, align 1
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ret void
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}
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; CHECK: stwcx.
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