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Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201333 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
2.1 KiB
LLVM
49 lines
2.1 KiB
LLVM
; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 -no-integrated-as | FileCheck %s
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; RUN: llc < %s -march=x86 -regalloc=basic -no-integrated-as | FileCheck %s
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; RUN: llc < %s -march=x86 -regalloc=greedy -no-integrated-as | FileCheck %s
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; The 1st, 2nd, 3rd and 5th registers must all be different. The registers
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; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
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; operand.
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;
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; CHECK: 1st=[[A1:%...]]
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; CHECK-NOT: [[A1]]
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; CHECK: 2nd=[[A2:%...]]
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; CHECK-NOT: [[A1]]
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; CHECK-NOT: [[A2]]
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; CHECK: 3rd=[[A3:%...]]
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; CHECK-NOT: [[A1]]
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; CHECK-NOT: [[A2]]
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; CHECK-NOT: [[A3]]
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; CHECK: 5th=[[A5:%...]]
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; CHECK-NOT: [[A1]]
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; CHECK-NOT: [[A5]]
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; CHECK: =4th
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; The 6th operand is an 8-bit register, and it mustn't alias the 1st and 5th.
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; CHECK: 1%e[[S1:.]]x
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; CHECK: 5%e[[S5:.]]x
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; CHECK-NOT: %[[S1]]
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; CHECK-NOT: %[[S5]]
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i386-apple-darwin8"
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%struct.foo = type { i32, i32, i8* }
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define i32 @get(%struct.foo* %c, i8* %state) nounwind {
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entry:
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%0 = getelementptr %struct.foo* %c, i32 0, i32 0 ; <i32*> [#uses=2]
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%1 = getelementptr %struct.foo* %c, i32 0, i32 1 ; <i32*> [#uses=2]
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%2 = getelementptr %struct.foo* %c, i32 0, i32 2 ; <i8**> [#uses=2]
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%3 = load i32* %0, align 4 ; <i32> [#uses=1]
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%4 = load i32* %1, align 4 ; <i32> [#uses=1]
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%5 = load i8* %state, align 1 ; <i8> [#uses=1]
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%asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#1st=$0 $1 2nd=$1 $2 3rd=$2 $4 5th=$4 $3=4th 1$0 1%eXx 5$4 5%eXx 6th=$5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3]
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%asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0 ; <i32> [#uses=1]
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%asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1 ; <i32> [#uses=1]
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store i32 %asmresult1, i32* %0
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%asmresult2 = extractvalue { i32, i32, i32, i32 } %asmtmp, 2 ; <i32> [#uses=1]
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store i32 %asmresult2, i32* %1
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ret i32 %asmresult
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}
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