mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 04:29:44 +00:00
38c6b58eec
Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201333 91177308-0d34-0410-b5e6-96231b3b80d8
128 lines
3.7 KiB
LLVM
128 lines
3.7 KiB
LLVM
; RUN: llc < %s -march=x86 -mcpu=core2 -no-integrated-as | FileCheck %s
|
|
|
|
define i32 @t1() nounwind {
|
|
entry:
|
|
%0 = tail call i32 asm sideeffect inteldialect "mov eax, $1\0A\09mov $0, eax", "=r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
|
|
ret i32 %0
|
|
; CHECK: t1
|
|
; CHECK: {{## InlineAsm Start|#APP}}
|
|
; CHECK: .intel_syntax
|
|
; CHECK: mov eax, ecx
|
|
; CHECK: mov ecx, eax
|
|
; CHECK: .att_syntax
|
|
; CHECK: {{## InlineAsm End|#NO_APP}}
|
|
}
|
|
|
|
define void @t2() nounwind {
|
|
entry:
|
|
call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
|
|
ret void
|
|
; CHECK: t2
|
|
; CHECK: {{## InlineAsm Start|#APP}}
|
|
; CHECK: .intel_syntax
|
|
; CHECK: mov eax, 1
|
|
; CHECK: .att_syntax
|
|
; CHECK: {{## InlineAsm End|#NO_APP}}
|
|
}
|
|
|
|
define void @t3(i32 %V) nounwind {
|
|
entry:
|
|
%V.addr = alloca i32, align 4
|
|
store i32 %V, i32* %V.addr, align 4
|
|
call void asm sideeffect inteldialect "mov eax, DWORD PTR [$0]", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %V.addr) nounwind
|
|
ret void
|
|
; CHECK: t3
|
|
; CHECK: {{## InlineAsm Start|#APP}}
|
|
; CHECK: .intel_syntax
|
|
; CHECK: mov eax, DWORD PTR {{[[esp]}}
|
|
; CHECK: .att_syntax
|
|
; CHECK: {{## InlineAsm End|#NO_APP}}
|
|
}
|
|
|
|
%struct.t18_type = type { i32, i32 }
|
|
|
|
define i32 @t18() nounwind {
|
|
entry:
|
|
%foo = alloca %struct.t18_type, align 4
|
|
%a = getelementptr inbounds %struct.t18_type* %foo, i32 0, i32 0
|
|
store i32 1, i32* %a, align 4
|
|
%b = getelementptr inbounds %struct.t18_type* %foo, i32 0, i32 1
|
|
store i32 2, i32* %b, align 4
|
|
call void asm sideeffect inteldialect "lea ebx, foo\0A\09mov eax, [ebx].0\0A\09mov [ebx].4, ecx", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
|
|
%b1 = getelementptr inbounds %struct.t18_type* %foo, i32 0, i32 1
|
|
%0 = load i32* %b1, align 4
|
|
ret i32 %0
|
|
; CHECK: t18
|
|
; CHECK: {{## InlineAsm Start|#APP}}
|
|
; CHECK: .intel_syntax
|
|
; CHECK: lea ebx, foo
|
|
; CHECK: mov eax, [ebx].0
|
|
; CHECK: mov [ebx].4, ecx
|
|
; CHECK: .att_syntax
|
|
; CHECK: {{## InlineAsm End|#NO_APP}}
|
|
}
|
|
|
|
define void @t19_helper() nounwind {
|
|
entry:
|
|
ret void
|
|
}
|
|
|
|
define void @t19() nounwind {
|
|
entry:
|
|
call void asm sideeffect inteldialect "call $0", "r,~{dirflag},~{fpsr},~{flags}"(void ()* @t19_helper) nounwind
|
|
ret void
|
|
; CHECK-LABEL: t19:
|
|
; CHECK: movl ${{_?}}t19_helper, %eax
|
|
; CHECK: {{## InlineAsm Start|#APP}}
|
|
; CHECK: .intel_syntax
|
|
; CHECK: call eax
|
|
; CHECK: .att_syntax
|
|
; CHECK: {{## InlineAsm End|#NO_APP}}
|
|
}
|
|
|
|
@results = global [2 x i32] [i32 3, i32 2], align 4
|
|
|
|
define i32* @t30() nounwind ssp {
|
|
entry:
|
|
%res = alloca i32*, align 4
|
|
call void asm sideeffect inteldialect "lea edi, dword ptr $0", "*m,~{edi},~{dirflag},~{fpsr},~{flags}"([2 x i32]* @results) nounwind
|
|
call void asm sideeffect inteldialect "mov dword ptr $0, edi", "=*m,~{dirflag},~{fpsr},~{flags}"(i32** %res) nounwind
|
|
%0 = load i32** %res, align 4
|
|
ret i32* %0
|
|
; CHECK-LABEL: t30:
|
|
; CHECK: {{## InlineAsm Start|#APP}}
|
|
; CHECK: .intel_syntax
|
|
; CHECK: lea edi, dword ptr [{{_?}}results]
|
|
; CHECK: .att_syntax
|
|
; CHECK: {{## InlineAsm End|#NO_APP}}
|
|
; CHECK: {{## InlineAsm Start|#APP}}
|
|
; CHECK: .intel_syntax
|
|
; CHECK: mov dword ptr [esp], edi
|
|
; CHECK: .att_syntax
|
|
; CHECK: {{## InlineAsm End|#NO_APP}}
|
|
; CHECK: movl (%esp), %eax
|
|
}
|
|
|
|
; Stack realignment plus MS inline asm that does *not* adjust the stack is no
|
|
; longer an error.
|
|
|
|
define i32 @t31() {
|
|
entry:
|
|
%val = alloca i32, align 64
|
|
store i32 -1, i32* %val, align 64
|
|
call void asm sideeffect inteldialect "mov dword ptr $0, esp", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %val) #1
|
|
%sp = load i32* %val, align 64
|
|
ret i32 %sp
|
|
; CHECK-LABEL: t31:
|
|
; CHECK: pushl %ebp
|
|
; CHECK: movl %esp, %ebp
|
|
; CHECK: andl $-64, %esp
|
|
; CHECK: {{## InlineAsm Start|#APP}}
|
|
; CHECK: .intel_syntax
|
|
; CHECK: mov dword ptr [esp], esp
|
|
; CHECK: .att_syntax
|
|
; CHECK: {{## InlineAsm End|#NO_APP}}
|
|
; CHECK: movl (%esp), %eax
|
|
; CHECK: ret
|
|
}
|