llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-27 13:30:05 +00:00

History

Evan Cheng 0e6a052331 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-18 20:57:22 +00:00
..
MCTargetDesc	Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down	2011-07-18 20:57:22 +00:00
TargetInfo
Alpha.h	Next round of MC refactoring. This patch factor MC table instantiations, MC	2011-07-14 20:59:42 +00:00
Alpha.td	Fix a ton of comment typos found by codespell. Patch by	2011-04-15 05:18:47 +00:00
AlphaAsmPrinter.cpp	move all the target's asmprinters into the main target. The piece	2010-11-14 18:43:56 +00:00
AlphaBranchSelector.cpp
AlphaCallingConv.td
AlphaFrameLowering.cpp	Teach frame lowering to ignore debug values after the terminators.	2011-01-13 21:28:52 +00:00
AlphaFrameLowering.h	Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.	2011-01-10 12:39:04 +00:00
AlphaInstrFormats.td
AlphaInstrInfo.cpp	Next round of MC refactoring. This patch factor MC table instantiations, MC	2011-07-14 20:59:42 +00:00
AlphaInstrInfo.h	Hide the call to InitMCInstrInfo into tblgen generated ctor.	2011-07-01 17:57:27 +00:00
AlphaInstrInfo.td	Fix a ton of comment typos found by codespell. Patch by	2011-04-15 05:18:47 +00:00
AlphaISelDAGToDAG.cpp	rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for	2010-12-21 02:38:05 +00:00
AlphaISelLowering.cpp	Add an intrinsic and codegen support for fused multiply-accumulate. The intent	2011-07-08 21:39:21 +00:00
AlphaISelLowering.h	Move Alpha from getRegClassForInlineAsmConstraint to	2011-06-29 19:40:01 +00:00
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaRegisterInfo.cpp	Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down	2011-07-18 20:57:22 +00:00
AlphaRegisterInfo.h	Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down	2011-07-18 20:57:22 +00:00
AlphaRegisterInfo.td	Use set operations instead of plain lists to enumerate register classes.	2011-06-15 23:28:14 +00:00
AlphaRelocations.h
AlphaSchedule.td
AlphaSelectionDAGInfo.cpp
AlphaSelectionDAGInfo.h
AlphaSubtarget.cpp	Next round of MC refactoring. This patch factor MC table instantiations, MC	2011-07-14 20:59:42 +00:00
AlphaSubtarget.h	Compute feature bits at time of MCSubtargetInfo initialization.	2011-07-07 07:07:08 +00:00
AlphaTargetMachine.cpp	Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.	2011-07-14 23:50:31 +00:00
AlphaTargetMachine.h	Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to	2011-06-30 01:53:36 +00:00
CMakeLists.txt	Major update to CMake build to reflect changes in r135219 in the	2011-07-15 00:40:52 +00:00
Makefile	Next round of MC refactoring. This patch factor MC table instantiations, MC	2011-07-14 20:59:42 +00:00
README.txt	Fix a ton of comment typos found by codespell. Patch by	2011-04-15 05:18:47 +00:00

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum across bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extensions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html