llvm-6502/lib/CodeGen
Jakob Stoklund Olesen 4a4bc3fba6 Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 18:50:24 +00:00
..
AsmPrinter add a comment about where this should eventually move. 2010-09-05 20:33:40 +00:00
PBQP Added initialisers for reduction rule counters. 2010-09-05 13:42:32 +00:00
SelectionDAG implement rdar://6653118 - fastisel should fold loads where possible. 2010-09-05 02:18:34 +00:00
AggressiveAntiDepBreaker.cpp Anti-dependency breaking needs to be careful not to use reserved regs 2010-09-02 17:12:55 +00:00
AggressiveAntiDepBreaker.h
Analysis.cpp
AntiDepBreaker.h
BranchFolding.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
BranchFolding.h
CalcSpillWeights.cpp Clean up debug output. 2010-08-12 18:50:55 +00:00
CallingConvLower.cpp
CMakeLists.txt Update CMake build. 2010-08-14 01:55:09 +00:00
CodePlacementOpt.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
CriticalAntiDepBreaker.cpp Anti-dependency breaking needs to be careful not to use reserved regs 2010-09-02 17:12:55 +00:00
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp Track liveness of unallocatable, unreserved registers in machine DCE. 2010-08-31 21:51:05 +00:00
DwarfEHPrepare.cpp Reapply commit 112702 which was speculatively reverted by echristo. 2010-09-03 08:31:48 +00:00
ELF.h
ELFCodeEmitter.cpp
ELFCodeEmitter.h
ELFWriter.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
ELFWriter.h Tidy some #includes and forward-declarations, and move the C binding code 2010-08-07 00:43:20 +00:00
GCMetadata.cpp zap dead code. 2010-09-04 18:12:00 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
IfConversion.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
InlineSpiller.cpp Clean up the Spiller.h interface. 2010-08-13 22:56:53 +00:00
IntrinsicLowering.cpp
LatencyPriorityQueue.cpp
LiveInterval.cpp Remove dead code. 2010-09-08 18:50:24 +00:00
LiveIntervalAnalysis.cpp PHI elimination shouldn't require machineloopinfo since it's used at -O0. Move the requirement to LiveIntervalAnalysis instead. Note this does not change the number of times machineloopinfo is computed. 2010-08-17 21:00:37 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Remove unused functions. 2010-08-16 17:18:20 +00:00
LLVMTargetMachine.cpp Stop using the dom frontier in DwarfEHPrepare by not promoting alloca's 2010-08-31 09:05:06 +00:00
LocalStackSlotAllocation.cpp Improve virtual frame base register allocation heuristics. 2010-08-31 17:58:19 +00:00
LowerSubregs.cpp Remove unused functions. 2010-08-16 17:18:20 +00:00
MachineBasicBlock.cpp Properly update MachineDominators when splitting critical edge. 2010-08-19 23:32:47 +00:00
MachineCSE.cpp Machine CSE preserves CFG. Pass manager was freeing machineloopinfo after machine cse before. 2010-08-17 20:57:42 +00:00
MachineDominators.cpp Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API. 2010-08-23 17:52:01 +00:00
MachineFunction.cpp
MachineFunctionAnalysis.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
MachineInstr.cpp
MachineLICM.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
MachineLoopInfo.cpp Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API. 2010-08-23 17:52:01 +00:00
MachineModuleInfo.cpp zap dead code. 2010-09-04 18:12:00 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp Update debug logs. 2010-08-19 23:33:02 +00:00
MachineSSAUpdater.cpp
MachineVerifier.cpp Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API. 2010-08-23 17:52:01 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizePHIs.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
Passes.cpp
PeepholeOptimizer.cpp Remove now unneeded command line flag that enables 'optimize compares.' 2010-08-27 20:39:09 +00:00
PHIElimination.cpp Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API. 2010-08-23 17:52:01 +00:00
PHIElimination.h PHI elimination shouldn't require machineloopinfo since it's used at -O0. Move the requirement to LiveIntervalAnalysis instead. Note this does not change the number of times machineloopinfo is computed. 2010-08-17 21:00:37 +00:00
PostRAHazardRecognizer.cpp
PostRASchedulerList.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
PreAllocSplitting.cpp Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API. 2010-08-23 17:52:01 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp Simplify eliminateFrameIndex() interface back down now that PEI doesn't need 2010-08-26 23:32:16 +00:00
PrologEpilogInserter.h Simplify eliminateFrameIndex() interface back down now that PEI doesn't need 2010-08-26 23:32:16 +00:00
PseudoSourceValue.cpp
README.txt
RegAllocFast.cpp previous patch was a little too tricky for its own good. Don't try to 2010-09-03 21:45:15 +00:00
RegAllocLinearScan.cpp Tweak to ignoring reserved regs. The allocator was occasionally still looking 2010-09-01 22:48:34 +00:00
RegAllocPBQP.cpp Added support for register allocators to record which intervals are spill intervals, and where the uses and defs of the original intervals were in the original code. 2010-09-02 08:27:00 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp The scavenger should just use getAllocatableSet() rather than reinventing it 2010-09-02 18:29:04 +00:00
RenderMachineFunction.cpp Added support for register allocators to record which intervals are spill intervals, and where the uses and defs of the original intervals were in the original code. 2010-09-02 08:27:00 +00:00
RenderMachineFunction.h Added support for register allocators to record which intervals are spill intervals, and where the uses and defs of the original intervals were in the original code. 2010-09-02 08:27:00 +00:00
ScheduleDAG.cpp
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp
ScheduleDAGInstrs.h
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp
ShrinkWrapping.cpp
SimpleRegisterCoalescing.cpp Teach RemoveCopyByCommutingDef to check all aliases, not just subregisters. 2010-09-01 22:15:35 +00:00
SimpleRegisterCoalescing.h Transpose the calculation of spill weights such that we are calculating one 2010-08-10 00:02:26 +00:00
SjLjEHPrepare.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
SlotIndexes.cpp
Spiller.cpp Clean up the Spiller.h interface. 2010-08-13 22:56:53 +00:00
Spiller.h Clean up the Spiller.h interface. 2010-08-13 22:56:53 +00:00
SplitKit.cpp Fix the msvc 2010 build. 2010-08-19 18:16:39 +00:00
SplitKit.h Thinking about it, we don't need MachineDominatorTree after all. The DomValue 2010-08-18 20:29:53 +00:00
Splitter.cpp
Splitter.h Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
StackProtector.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
StackSlotColoring.cpp remove dead proto 2010-08-28 03:45:03 +00:00
StrongPHIElimination.cpp Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API. 2010-08-23 17:52:01 +00:00
TailDuplication.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
TargetInstrInfoImpl.cpp
TargetLoweringObjectFileImpl.cpp two changes: 2010-08-30 18:12:35 +00:00
TwoAddressInstructionPass.cpp Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API. 2010-08-23 17:52:01 +00:00
UnreachableBlockElim.cpp Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API. 2010-08-23 17:52:01 +00:00
VirtRegMap.cpp
VirtRegMap.h Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
VirtRegRewriter.cpp Don't add <imp-def> operands during register rewriting. 2010-09-07 22:38:45 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.