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https://github.com/c64scene-ar/llvm-6502.git
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f73bae1b73
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24513 91177308-0d34-0410-b5e6-96231b3b80d8
371 lines
14 KiB
C++
371 lines
14 KiB
C++
//===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Duraid Madina and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the IA64ISelLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "IA64ISelLowering.h"
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#include "IA64MachineFunctionInfo.h"
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#include "IA64TargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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using namespace llvm;
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IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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// register class for general registers
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addRegisterClass(MVT::i64, IA64::GRRegisterClass);
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// register class for FP registers
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addRegisterClass(MVT::f64, IA64::FPRegisterClass);
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// register class for predicate registers
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addRegisterClass(MVT::i1, IA64::PRRegisterClass);
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setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
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setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
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setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
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setSetCCResultType(MVT::i1);
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setShiftAmountType(MVT::i64);
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setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
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setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand);
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setOperationAction(ISD::FREM , MVT::f32 , Expand);
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setOperationAction(ISD::FREM , MVT::f64 , Expand);
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setOperationAction(ISD::UREM , MVT::f32 , Expand);
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setOperationAction(ISD::UREM , MVT::f64 , Expand);
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setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
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setOperationAction(ISD::MEMSET , MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
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setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
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setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
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// We don't support sin/cos/sqrt
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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//IA64 has these, but they are not implemented
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
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computeRegisterProperties();
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addLegalFPImmediate(+0.0);
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addLegalFPImmediate(+1.0);
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}
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/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
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static bool isFloatingPointZero(SDOperand Op) {
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if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
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return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
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else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
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// Maybe this has already been legalized into the constant pool?
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
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if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
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return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
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}
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return false;
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}
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std::vector<SDOperand>
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IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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std::vector<SDOperand> ArgValues;
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//
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// add beautiful description of IA64 stack frame format
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// here (from intel 24535803.pdf most likely)
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//
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
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SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
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RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
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MachineBasicBlock& BB = MF.front();
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unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
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IA64::r36, IA64::r37, IA64::r38, IA64::r39};
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unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
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IA64::F12,IA64::F13,IA64::F14, IA64::F15};
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unsigned argVreg[8];
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unsigned argPreg[8];
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unsigned argOpc[8];
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unsigned used_FPArgs = 0; // how many FP args have been used so far?
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unsigned ArgOffset = 0;
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int count = 0;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
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{
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SDOperand newroot, argt;
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if(count < 8) { // need to fix this logic? maybe.
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switch (getValueType(I->getType())) {
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default:
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assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
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case MVT::f32:
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// fixme? (well, will need to for weird FP structy stuff,
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// see intel ABI docs)
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case MVT::f64:
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//XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
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MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
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// floating point args go into f8..f15 as-needed, the increment
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argVreg[count] = // is below..:
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MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
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// FP args go into f8..f15 as needed: (hence the ++)
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argPreg[count] = args_FP[used_FPArgs++];
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argOpc[count] = IA64::FMOV;
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argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
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MVT::f64);
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if (I->getType() == Type::FloatTy)
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argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
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break;
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case MVT::i1: // NOTE: as far as C abi stuff goes,
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// bools are just boring old ints
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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//XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
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MF.addLiveIn(args_int[count]); // mark this register as liveIn
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argVreg[count] =
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MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
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argPreg[count] = args_int[count];
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argOpc[count] = IA64::MOV;
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argt = newroot =
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DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
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if ( getValueType(I->getType()) != MVT::i64)
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argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
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newroot);
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break;
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}
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} else { // more than 8 args go into the frame
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// Create the frame index object for this incoming parameter...
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ArgOffset = 16 + 8 * (count - 8);
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int FI = MFI->CreateFixedObject(8, ArgOffset);
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// Create the SelectionDAG nodes corresponding to a load
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//from this parameter
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
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argt = newroot = DAG.getLoad(getValueType(I->getType()),
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DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
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}
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++count;
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DAG.setRoot(newroot.getValue(1));
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ArgValues.push_back(argt);
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}
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// Create a vreg to hold the output of (what will become)
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// the "alloc" instruction
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VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
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BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR);
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// we create a PSEUDO_ALLOC (pseudo)instruction for now
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/*
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BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
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// hmm:
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BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
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BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
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// ..hmm.
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BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
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// hmm:
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BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
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BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
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// ..hmm.
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*/
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unsigned tempOffset=0;
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// if this is a varargs function, we simply lower llvm.va_start by
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// pointing to the first entry
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if(F.isVarArg()) {
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tempOffset=0;
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VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
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}
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// here we actually do the moving of args, and store them to the stack
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// too if this is a varargs function:
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for (int i = 0; i < count && i < 8; ++i) {
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BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]);
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if(F.isVarArg()) {
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// if this is a varargs function, we copy the input registers to the stack
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int FI = MFI->CreateFixedObject(8, tempOffset);
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tempOffset+=8; //XXX: is it safe to use r22 like this?
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BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI);
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// FIXME: we should use st8.spill here, one day
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BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]);
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}
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}
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// Finally, inform the code generator which regs we return values in.
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// (see the ISD::RET: case in the instruction selector)
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switch (getValueType(F.getReturnType())) {
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default: assert(0 && "i have no idea where to return this type!");
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case MVT::isVoid: break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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MF.addLiveOut(IA64::r8);
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break;
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case MVT::f32:
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case MVT::f64:
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MF.addLiveOut(IA64::F8);
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break;
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}
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return ArgValues;
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}
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std::pair<SDOperand, SDOperand>
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IA64TargetLowering::LowerCallTo(SDOperand Chain,
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const Type *RetTy, bool isVarArg,
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unsigned CallingConv, bool isTailCall,
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SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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unsigned NumBytes = 16;
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unsigned outRegsUsed = 0;
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if (Args.size() > 8) {
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NumBytes += (Args.size() - 8) * 8;
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outRegsUsed = 8;
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} else {
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outRegsUsed = Args.size();
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}
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// FIXME? this WILL fail if we ever try to pass around an arg that
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// consumes more than a single output slot (a 'real' double, int128
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// some sort of aggregate etc.), as we'll underestimate how many 'outX'
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// registers we use. Hopefully, the assembler will notice.
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MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
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std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
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Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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std::vector<SDOperand> args_to_use;
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for (unsigned i = 0, e = Args.size(); i != e; ++i)
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{
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switch (getValueType(Args[i].second)) {
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default: assert(0 && "unexpected argument type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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//promote to 64-bits, sign/zero extending based on type
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//of the argument
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if(Args[i].second->isSigned())
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Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64,
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Args[i].first);
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else
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Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64,
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Args[i].first);
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break;
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case MVT::f32:
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//promote to 64-bits
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Args[i].first = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Args[i].first);
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case MVT::f64:
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case MVT::i64:
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break;
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}
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args_to_use.push_back(Args[i].first);
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}
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std::vector<MVT::ValueType> RetVals;
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MVT::ValueType RetTyVT = getValueType(RetTy);
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if (RetTyVT != MVT::isVoid)
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RetVals.push_back(RetTyVT);
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RetVals.push_back(MVT::Other);
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SDOperand TheCall = SDOperand(DAG.getCall(RetVals, Chain,
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Callee, args_to_use), 0);
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Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
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Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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return std::make_pair(TheCall, Chain);
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}
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SDOperand
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IA64TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG) {
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// vastart just stores the address of the VarArgsFrameIndex slot.
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SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
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return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR,
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VAListP, DAG.getSrcValue(VAListV));
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}
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std::pair<SDOperand,SDOperand> IA64TargetLowering::
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LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG) {
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MVT::ValueType ArgVT = getValueType(ArgTy);
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SDOperand Val = DAG.getLoad(MVT::i64, Chain,
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VAListP, DAG.getSrcValue(VAListV));
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SDOperand Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), Val,
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DAG.getSrcValue(NULL));
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unsigned Amt;
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if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
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Amt = 8;
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else {
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assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
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"Other types should have been promoted for varargs!");
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Amt = 8;
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}
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Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
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DAG.getConstant(Amt, Val.getValueType()));
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Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
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Val, VAListP, DAG.getSrcValue(VAListV));
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return std::make_pair(Result, Chain);
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}
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std::pair<SDOperand, SDOperand> IA64TargetLowering::
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LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG) {
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assert(0 && "LowerFrameReturnAddress unimplemented");
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abort();
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}
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