llvm-6502/lib/Target/Sparc
Chris Lattner ea7fd96698 add missing file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81881 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 18:03:13 +00:00
..
AsmPrinter several major improvements to the sparc backend: support for weak linkage 2009-09-15 17:46:24 +00:00
TargetInfo Normalize target registration code. 2009-07-31 18:16:53 +00:00
CMakeLists.txt Normalize makefile comments and sort cmake file lists. 2009-08-31 13:05:24 +00:00
DelaySlotFiller.cpp
FPMover.cpp remove various std::ostream version of printing methods from 2009-08-23 03:41:05 +00:00
Makefile
README.txt
Sparc.h
Sparc.td
SparcCallingConv.td
SparcInstrFormats.td
SparcInstrInfo.cpp several major improvements to the sparc backend: support for weak linkage 2009-09-15 17:46:24 +00:00
SparcInstrInfo.h several major improvements to the sparc backend: support for weak linkage 2009-09-15 17:46:24 +00:00
SparcInstrInfo.td several major improvements to the sparc backend: support for weak linkage 2009-09-15 17:46:24 +00:00
SparcISelDAGToDAG.cpp several major improvements to the sparc backend: support for weak linkage 2009-09-15 17:46:24 +00:00
SparcISelLowering.cpp several major improvements to the sparc backend: support for weak linkage 2009-09-15 17:46:24 +00:00
SparcISelLowering.h several major improvements to the sparc backend: support for weak linkage 2009-09-15 17:46:24 +00:00
SparcMachineFunctionInfo.h add missing file 2009-09-15 18:03:13 +00:00
SparcMCAsmInfo.cpp Add source debug information to the Sparc code generator. 2009-09-08 12:47:30 +00:00
SparcMCAsmInfo.h Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. 2009-08-22 20:48:53 +00:00
SparcRegisterInfo.cpp Add source debug information to the Sparc code generator. 2009-09-08 12:47:30 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td several major improvements to the sparc backend: support for weak linkage 2009-09-15 17:46:24 +00:00
SparcSubtarget.cpp Normalize Subtarget constructors to take a target triple string instead of 2009-08-02 22:11:08 +00:00
SparcSubtarget.h Normalize Subtarget constructors to take a target triple string instead of 2009-08-02 22:11:08 +00:00
SparcTargetMachine.cpp Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. 2009-08-22 20:48:53 +00:00
SparcTargetMachine.h Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple 2009-08-12 07:22:17 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots