Tim Northover f52efce72d ARM: implement MRS/MSR (banked reg) system instructions. ... These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215700 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-15 10:47:12 +00:00
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addrmode2-reencoding.txt
arm-LDREXD-reencoding.txt
arm-STREXD-reencoding.txt
arm-tests.txt
arm-thumb-trustzone.txt
arm-trustzone.txt
basic-arm-instructions-v8.txt
basic-arm-instructions.txt
crc32-thumb.txt
crc32.txt
fp-armv8.txt
fp-encoding.txt
hex-immediates.txt
invalid-armv7.txt
invalid-armv8.txt
invalid-because-armv7.txt
invalid-FSTMX-arm.txt
invalid-IT-CC15.txt
invalid-thumb-MSR-MClass.txt
invalid-thumbv7-xfail.txt
invalid-thumbv7.txt
invalid-thumbv8.txt
ldrd-armv4.txt
lit.local.cfg
load-store-acquire-release-v8-thumb.txt
load-store-acquire-release-v8.txt
marked-up-thumb.txt
memory-arm-instructions.txt
move-banked-regs-arm.txt
move-banked-regs-thumb.txt
neon-crypto.txt
neon-tests.txt
neon-v8.txt
neon.txt
neont2.txt
neont-VLD-reencoding.txt
neont-VST-reencoding.txt
thumb1.txt
thumb2-v8.txt
thumb2.txt
thumb-fp-armv8.txt
thumb-MSR-MClass.txt
thumb-neon-crypto.txt
thumb-neon-v8.txt
thumb-printf.txt
thumb-tests.txt
thumb-v8.txt
unpredictable-ADC-arm.txt
unpredictable-ADDREXT3-arm.txt
unpredictable-AExtI-arm.txt
unpredictable-AI1cmp-arm.txt
unpredictable-BFI.txt
unpredictable-LDR-arm.txt
unpredictable-LDRD-arm.txt
unpredictable-LSL-regform.txt
unpredictable-MRRC2-arm.txt
unpredictable-MRS-arm.txt
unpredictable-MUL-arm.txt
unpredictable-RSC-arm.txt
unpredictable-SEL-arm.txt
unpredictable-SHADD16-arm.txt
unpredictable-SSAT-arm.txt
unpredictable-STRBrs-arm.txt
unpredictable-swp-arm.txt
unpredictable-UQADD8-arm.txt
unpredictables-thumb.txt
vfp4.txt