llvm-6502/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
James Molloy ea029d5b15 Allow only disassembling of M-class MSR masks that the assembler knows how to assemble back.
Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed.

Patch by Petr Pavlu!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214505 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 12:42:11 +00:00

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# RUN: not llvm-mc -disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m3 2>&1 | FileCheck %s
#------------------------------------------------------------------------------
# Undefined encodings for mrs
#------------------------------------------------------------------------------
# invalid SYSm
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0xef 0xf3 0x80 0x80]
[0xef 0xf3 0x80 0x80]
#------------------------------------------------------------------------------
# Undefined encodings for msr
#------------------------------------------------------------------------------
# invalid mask = '00'
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x80 0xf3 0x00 0x80]
[0x80 0xf3 0x00 0x80]
# invalid mask = '11' with SYSm not in {0..3}
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x80 0xf3 0x04 0x8c]
[0x80 0xf3 0x04 0x8c]
# invalid mask = '01' (Cortex-M3 does not have the DSP extension)
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x80 0xf3 0x00 0x84]
[0x80 0xf3 0x00 0x84]
# invalid SYSm
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x80 0xf3 0x80 0x88]
[0x80 0xf3 0x80 0x88]