llvm-6502/test/CodeGen
Hans Wennborg 12447575dc Fix test/CodeGen/X86/tls-pie.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156612 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 10:19:54 +00:00
..
ARM ARM: peephole optimization to remove cmp instruction 2012-05-11 01:30:47 +00:00
CellSPU Flip the new block-placement pass to be on by default. 2012-04-16 13:49:17 +00:00
CPP
Generic change the objectsize intrinsic signature: add a 3rd parameter to denote the maximum runtime performance penalty that the user is willing to accept. 2012-05-09 15:52:43 +00:00
Hexagon Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
MBlaze
Mips Add support for the 'X' inline asm operand modifier. 2012-05-10 21:48:22 +00:00
MSP430
NVPTX This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. 2012-05-04 20:18:50 +00:00
PowerPC Remove dead SD nodes after the combining pass. Fixes PR12201. 2012-04-16 03:33:22 +00:00
PTX
SPARC Regression test for PR2960. 2012-05-01 11:11:34 +00:00
Thumb Make test less fragile. 2012-04-27 20:48:18 +00:00
Thumb2 Added a regress test for the bug #9964 before close it. 2012-05-09 19:07:04 +00:00
X86 Fix test/CodeGen/X86/tls-pie.ll. 2012-05-11 10:19:54 +00:00
XCore Flip the new block-placement pass to be on by default. 2012-04-16 13:49:17 +00:00