mirror of
https://github.com/c64scene-ar/llvm-6502.git
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instructions. This simplifies instruction printing and disassembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120333 91177308-0d34-0410-b5e6-96231b3b80d8
670 lines
21 KiB
C++
670 lines
21 KiB
C++
//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an ARM MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "ARMBaseInfo.h"
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#include "ARMInstPrinter.h"
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#include "ARMAddressingModes.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define GET_INSTRUCTION_NAME
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#include "ARMGenAsmWriter.inc"
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StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
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return getInstructionName(Opcode);
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}
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void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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unsigned Opcode = MI->getOpcode();
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// Check for MOVs and print canonical forms, instead.
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if (Opcode == ARM::MOVs) {
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// FIXME: Thumb variants?
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const MCOperand &Dst = MI->getOperand(0);
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const MCOperand &MO1 = MI->getOperand(1);
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const MCOperand &MO2 = MI->getOperand(2);
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const MCOperand &MO3 = MI->getOperand(3);
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O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
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printSBitModifierOperand(MI, 6, O);
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printPredicateOperand(MI, 4, O);
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O << '\t' << getRegisterName(Dst.getReg())
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<< ", " << getRegisterName(MO1.getReg());
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if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
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return;
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O << ", ";
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if (MO2.getReg()) {
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O << getRegisterName(MO2.getReg());
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assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
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} else {
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O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
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}
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return;
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}
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// A8.6.123 PUSH
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if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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O << '\t' << "push";
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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return;
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}
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// A8.6.122 POP
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if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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O << '\t' << "pop";
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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return;
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}
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// A8.6.355 VPUSH
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if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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O << '\t' << "vpush";
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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return;
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}
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// A8.6.354 VPOP
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if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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O << '\t' << "vpop";
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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return;
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}
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printInstruction(MI, O);
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}
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void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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unsigned Reg = Op.getReg();
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O << getRegisterName(Reg);
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} else if (Op.isImm()) {
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O << '#' << Op.getImm();
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} else {
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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O << *Op.getExpr();
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}
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}
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static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
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const MCAsmInfo *MAI) {
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// Break it up into two parts that make up a shifter immediate.
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V = ARM_AM::getSOImmVal(V);
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assert(V != -1 && "Not a valid so_imm value!");
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unsigned Imm = ARM_AM::getSOImmValImm(V);
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unsigned Rot = ARM_AM::getSOImmValRot(V);
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// Print low-level immediate formation info, per
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// A5.1.3: "Data-processing operands - Immediate".
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if (Rot) {
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O << "#" << Imm << ", " << Rot;
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// Pretty printed version.
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if (CommentStream)
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*CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
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} else {
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O << "#" << Imm;
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}
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}
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/// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
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/// immediate in bits 0-7.
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void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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assert(MO.isImm() && "Not a valid so_imm value!");
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printSOImm(O, MO.getImm(), CommentStream, &MAI);
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}
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// so_reg is a 4-operand unit corresponding to register forms of the A5.1
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// "Addressing Mode 1 - Data-processing operands" forms. This includes:
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// REG 0 0 - e.g. R5
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// REG REG 0,SH_OPC - e.g. R5, ROR R3
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// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
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void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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const MCOperand &MO3 = MI->getOperand(OpNum+2);
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O << getRegisterName(MO1.getReg());
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// Print the shift opc.
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ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
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O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
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if (MO2.getReg()) {
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O << ' ' << getRegisterName(MO2.getReg());
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assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
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} else if (ShOpc != ARM_AM::rrx) {
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O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
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}
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}
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void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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const MCOperand &MO2 = MI->getOperand(Op+1);
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const MCOperand &MO3 = MI->getOperand(Op+2);
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if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
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printOperand(MI, Op, O);
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return;
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}
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O << "[" << getRegisterName(MO1.getReg());
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if (!MO2.getReg()) {
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if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
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O << ", #"
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
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<< ARM_AM::getAM2Offset(MO3.getImm());
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O << "]";
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return;
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}
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O << ", "
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
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<< getRegisterName(MO2.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
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O << ", "
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<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
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<< " #" << ShImm;
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O << "]";
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}
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void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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if (!MO1.getReg()) {
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unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
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O << '#'
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
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<< ImmOffs;
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return;
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}
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O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
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<< getRegisterName(MO1.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
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O << ", "
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<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
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<< " #" << ShImm;
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}
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void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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const MCOperand &MO3 = MI->getOperand(OpNum+2);
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O << '[' << getRegisterName(MO1.getReg());
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if (MO2.getReg()) {
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O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
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<< getRegisterName(MO2.getReg()) << ']';
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return;
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}
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if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
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O << ", #"
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
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<< ImmOffs;
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O << ']';
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}
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void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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if (MO1.getReg()) {
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O << (char)ARM_AM::getAM3Op(MO2.getImm())
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<< getRegisterName(MO1.getReg());
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return;
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}
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unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
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O << '#'
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
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<< ImmOffs;
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}
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void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
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.getImm());
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O << ARM_AM::getAMSubModeStr(Mode);
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}
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void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
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printOperand(MI, OpNum, O);
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return;
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}
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O << "[" << getRegisterName(MO1.getReg());
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if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
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O << ", #"
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
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<< ImmOffs * 4;
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}
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O << "]";
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}
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void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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O << "[" << getRegisterName(MO1.getReg());
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if (MO2.getImm()) {
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// FIXME: Both darwin as and GNU as violate ARM docs here.
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O << ", :" << (MO2.getImm() << 3);
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}
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O << "]";
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}
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void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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if (MO.getReg() == 0)
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O << "!";
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else
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O << ", " << getRegisterName(MO.getReg());
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}
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void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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uint32_t v = ~MO.getImm();
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int32_t lsb = CountTrailingZeros_32(v);
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int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
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assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
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O << '#' << lsb << ", #" << width;
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}
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void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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unsigned val = MI->getOperand(OpNum).getImm();
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O << ARM_MB::MemBOptToString(val);
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}
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void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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unsigned ShiftOp = MI->getOperand(OpNum).getImm();
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ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
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switch (Opc) {
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case ARM_AM::no_shift:
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return;
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case ARM_AM::lsl:
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O << ", lsl #";
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break;
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case ARM_AM::asr:
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O << ", asr #";
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break;
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default:
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assert(0 && "unexpected shift opcode for shift immediate operand");
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}
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O << ARM_AM::getSORegOffset(ShiftOp);
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}
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void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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O << "{";
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for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
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if (i != OpNum) O << ", ";
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O << getRegisterName(MI->getOperand(i).getReg());
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}
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O << "}";
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}
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void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNum);
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if (Op.getImm())
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O << "be";
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else
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O << "le";
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}
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void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNum);
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unsigned option = Op.getImm();
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unsigned mode = option & 31;
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bool changemode = option >> 5 & 1;
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unsigned AIF = option >> 6 & 7;
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unsigned imod = option >> 9 & 3;
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if (imod == 2)
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O << "ie";
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else if (imod == 3)
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O << "id";
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O << '\t';
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if (imod > 1) {
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if (AIF & 4) O << 'a';
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if (AIF & 2) O << 'i';
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if (AIF & 1) O << 'f';
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if (AIF > 0 && changemode) O << ", ";
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}
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if (changemode)
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O << '#' << mode;
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}
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void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNum);
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unsigned Mask = Op.getImm();
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if (Mask) {
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O << '_';
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if (Mask & 8) O << 'f';
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if (Mask & 4) O << 's';
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if (Mask & 2) O << 'x';
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if (Mask & 1) O << 'c';
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}
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}
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void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNum);
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O << '#';
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if (Op.getImm() < 0)
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O << '-' << (-Op.getImm() - 1);
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else
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O << Op.getImm();
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}
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void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
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if (CC != ARMCC::AL)
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O << ARMCondCodeToString(CC);
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}
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void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
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O << ARMCondCodeToString(CC);
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}
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void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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if (MI->getOperand(OpNum).getReg()) {
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assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
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"Expect ARM CPSR register!");
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O << 's';
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}
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}
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void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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O << MI->getOperand(OpNum).getImm();
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}
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void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
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}
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void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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O << "#" << MI->getOperand(OpNum).getImm() * 4;
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}
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void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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// (3 - the number of trailing zeros) is the number of then / else.
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unsigned Mask = MI->getOperand(OpNum).getImm();
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unsigned CondBit0 = Mask >> 4 & 1;
|
|
unsigned NumTZ = CountTrailingZeros_32(Mask);
|
|
assert(NumTZ <= 3 && "Invalid IT mask!");
|
|
for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
|
|
bool T = ((Mask >> Pos) & 1) == CondBit0;
|
|
if (T)
|
|
O << 't';
|
|
else
|
|
O << 'e';
|
|
}
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(Op);
|
|
const MCOperand &MO2 = MI->getOperand(Op+1);
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
O << ", " << getRegisterName(MO2.getReg()) << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O,
|
|
unsigned Scale) {
|
|
const MCOperand &MO1 = MI->getOperand(Op);
|
|
const MCOperand &MO2 = MI->getOperand(Op+1);
|
|
const MCOperand &MO3 = MI->getOperand(Op+2);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, Op, O);
|
|
return;
|
|
}
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
if (MO3.getReg())
|
|
O << ", " << getRegisterName(MO3.getReg());
|
|
else if (unsigned ImmOffs = MO2.getImm())
|
|
O << ", #" << ImmOffs * Scale;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
printThumbAddrModeRI5Operand(MI, Op, O, 1);
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
printThumbAddrModeRI5Operand(MI, Op, O, 2);
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
printThumbAddrModeRI5Operand(MI, Op, O, 4);
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(Op);
|
|
const MCOperand &MO2 = MI->getOperand(Op+1);
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
if (unsigned ImmOffs = MO2.getImm())
|
|
O << ", #" << ImmOffs*4;
|
|
O << "]";
|
|
}
|
|
|
|
// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
|
|
// register with shift forms.
|
|
// REG 0 0 - e.g. R5
|
|
// REG IMM, SH_OPC - e.g. R5, LSL #3
|
|
void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
unsigned Reg = MO1.getReg();
|
|
O << getRegisterName(Reg);
|
|
|
|
// Print the shift opc.
|
|
assert(MO2.isImm() && "Not a valid t2_so_reg value!");
|
|
ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
|
|
O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
|
|
if (ShOpc != ARM_AM::rrx)
|
|
O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, OpNum, O);
|
|
return;
|
|
}
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm();
|
|
bool isSub = OffImm < 0;
|
|
// Special value for #-0. All others are normal.
|
|
if (OffImm == INT32_MIN)
|
|
OffImm = 0;
|
|
if (isSub)
|
|
O << ", #-" << -OffImm;
|
|
else if (OffImm > 0)
|
|
O << ", #" << OffImm;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm();
|
|
// Don't print +0.
|
|
if (OffImm < 0)
|
|
O << ", #-" << -OffImm;
|
|
else if (OffImm > 0)
|
|
O << ", #" << OffImm;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm() / 4;
|
|
// Don't print +0.
|
|
if (OffImm < 0)
|
|
O << ", #-" << -OffImm * 4;
|
|
else if (OffImm > 0)
|
|
O << ", #" << OffImm * 4;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
int32_t OffImm = (int32_t)MO1.getImm();
|
|
// Don't print +0.
|
|
if (OffImm < 0)
|
|
O << "#-" << -OffImm;
|
|
else if (OffImm > 0)
|
|
O << "#" << OffImm;
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
int32_t OffImm = (int32_t)MO1.getImm() / 4;
|
|
// Don't print +0.
|
|
if (OffImm < 0)
|
|
O << "#-" << -OffImm * 4;
|
|
else if (OffImm > 0)
|
|
O << "#" << OffImm * 4;
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
const MCOperand &MO3 = MI->getOperand(OpNum+2);
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
|
|
assert(MO2.getReg() && "Invalid so_reg load / store address!");
|
|
O << ", " << getRegisterName(MO2.getReg());
|
|
|
|
unsigned ShAmt = MO3.getImm();
|
|
if (ShAmt) {
|
|
assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
|
|
O << ", lsl #" << ShAmt;
|
|
}
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << '#' << (float)MI->getOperand(OpNum).getFPImm();
|
|
}
|
|
|
|
void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << '#' << MI->getOperand(OpNum).getFPImm();
|
|
}
|
|
|
|
void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned EncodedImm = MI->getOperand(OpNum).getImm();
|
|
unsigned EltBits;
|
|
uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
|
|
O << "#0x" << utohexstr(Val);
|
|
}
|