Benjamin Kramer 1386e9b7b1 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. ... This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8		2012-05-29 19:05:25 +00:00
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ARM	These tests used intrinsics with the wrong prototype. They weren't caught because	2012-05-27 19:35:41 +00:00
CellSPU
CPP
Generic	revert my previous patches that introduced an additional parameter to the objectsize intrinsic.	2012-05-22 15:25:31 +00:00
Hexagon
MBlaze
Mips	Turn on mips16 pseudo op when compiling for mips16.	2012-05-24 18:37:43 +00:00
MSP430	These tests used intrinsics with the wrong prototype. They weren't caught because	2012-05-27 19:35:41 +00:00
NVPTX	Add llvm.fabs intrinsic.	2012-05-28 21:48:37 +00:00
PowerPC
SPARC
Thumb
Thumb2	Add a test case for global live range splitting.	2012-05-23 23:42:23 +00:00
X86	Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.	2012-05-29 19:05:25 +00:00
XCore