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https://github.com/c64scene-ar/llvm-6502.git
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63cc527fbc
We use the same constraints as GCC, including those that are slightly insane for inline assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77899 91177308-0d34-0410-b5e6-96231b3b80d8
39 lines
986 B
LLVM
39 lines
986 B
LLVM
; RUN: llvm-as < %s | llc -march=bfin | FileCheck %s
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; Standard "r"
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; CHECK: r0 = r0 + r1;
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define i32 @add_r(i32 %A, i32 %B) {
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%R = call i32 asm "$0 = $1 + $2;", "=r,r,r"( i32 %A, i32 %B ) nounwind
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ret i32 %R
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}
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; Target "d"
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; CHECK: r0 = r0 - r1;
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define i32 @add_d(i32 %A, i32 %B) {
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%R = call i32 asm "$0 = $1 - $2;", "=d,d,d"( i32 %A, i32 %B ) nounwind
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ret i32 %R
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}
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; Target "a" for P-regs
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; CHECK: p0 = (p0 + p1) << 1;
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define i32 @add_a(i32 %A, i32 %B) {
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%R = call i32 asm "$0 = ($1 + $2) << 1;", "=a,a,a"( i32 %A, i32 %B ) nounwind
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ret i32 %R
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}
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; Target "z" for P0, P1, P2. This is not a real regclass
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; CHECK: p0 = (p0 + p1) << 2;
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define i32 @add_Z(i32 %A, i32 %B) {
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%R = call i32 asm "$0 = ($1 + $2) << 2;", "=z,z,z"( i32 %A, i32 %B ) nounwind
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ret i32 %R
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}
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; Target "C" for CC. This is a single register
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; CHECK: cc = p0 < p1;
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; CHECK: r0 = cc;
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define i32 @add_C(i32 %A, i32 %B) {
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%R = call i32 asm "$0 = $1 < $2;", "=C,z,z"( i32 %A, i32 %B ) nounwind
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ret i32 %R
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}
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