Ahmed Bougacha 14fe2e6948 [AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR". ... r208210 introduced an optimization that improves the vector select codegen by doing the setcc on vectors directly. This is a problem they the setcc operands are i1s, because the optimization would create vectors of i1, which aren't legal. Part of PR21549. Differential Revision: http://reviews.llvm.org/D6308 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223075 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-01 20:59:00 +00:00
..
AArch64	[AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR".	2014-12-01 20:59:00 +00:00
ARM	ARM: lower tail calls correctly when using GHC calling convention.	2014-12-01 17:46:39 +00:00
CPP
Generic	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Hexagon	Handle ctor/init_array initialization.	2014-11-03 14:56:05 +00:00
Inputs	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Mips	[mips][micromips] Use call instructions with short delay slots	2014-11-25 10:50:00 +00:00
MSP430
NVPTX	[NVPTX] Add NVPTXLowerStructArgs pass	2014-11-05 18:19:30 +00:00
PowerPC	[PowerPC] Fix unwind info with dynamic stack realignment	2014-12-01 09:42:32 +00:00
R600	R600/SI: Fix assertion on sign extend of 3 vectors	2014-11-28 22:51:38 +00:00
SPARC
SystemZ
Thumb	[Thumb1] Re-write emitThumbRegPlusImmediate	2014-11-17 11:18:10 +00:00
Thumb2	ARM: allow constpool entry to be moved to the user's block in all cases.	2014-11-13 17:58:53 +00:00
X86	Revert r223049, r223050 and r223051 while investigating test failures.	2014-12-01 17:36:43 +00:00
XCore	Fix a bit of confusion about .set and produce more readable assembly.	2014-10-21 01:17:30 +00:00