mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
364 lines
11 KiB
LLVM
364 lines
11 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
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; Stackmap Header: no constants - 6 callsites
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; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
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; CHECK-NEXT: __LLVM_StackMaps:
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; Header
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 0
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; Num Functions
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; CHECK-NEXT: .long 8
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; Num LargeConstants
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; CHECK-NEXT: .long 0
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; Num Callsites
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; CHECK-NEXT: .long 8
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; Functions and stack size
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; CHECK-NEXT: .quad _test
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; CHECK-NEXT: .quad 16
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; CHECK-NEXT: .quad _property_access1
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; CHECK-NEXT: .quad 16
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; CHECK-NEXT: .quad _property_access2
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; CHECK-NEXT: .quad 32
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; CHECK-NEXT: .quad _property_access3
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; CHECK-NEXT: .quad 32
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; CHECK-NEXT: .quad _anyreg_test1
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; CHECK-NEXT: .quad 16
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; CHECK-NEXT: .quad _anyreg_test2
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; CHECK-NEXT: .quad 16
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; CHECK-NEXT: .quad _patchpoint_spilldef
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; CHECK-NEXT: .quad 112
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; CHECK-NEXT: .quad _patchpoint_spillargs
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; CHECK-NEXT: .quad 128
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; test
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; CHECK-LABEL: .long L{{.*}}-_test
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; CHECK-NEXT: .short 0
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; 3 locations
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; CHECK-NEXT: .short 3
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; Loc 0: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 2: Constant 3
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 3
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define i64 @test() nounwind ssp uwtable {
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entry:
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call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3)
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ret i64 0
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}
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; property access 1 - %obj is an anyreg call argument and should therefore be in a register
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; CHECK-LABEL: .long L{{.*}}-_property_access1
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
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entry:
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%f = inttoptr i64 281474417671919 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj)
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ret i64 %ret
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}
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; property access 2 - %obj is an anyreg call argument and should therefore be in a register
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; CHECK-LABEL: .long L{{.*}}-_property_access2
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @property_access2() nounwind ssp uwtable {
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entry:
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%obj = alloca i64, align 8
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%f = inttoptr i64 281474417671919 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj)
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ret i64 %ret
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}
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; property access 3 - %obj is a frame index
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; CHECK-LABEL: .long L{{.*}}-_property_access3
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Direct FP - 8
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 29
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; CHECK-NEXT: .long -8
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define i64 @property_access3() nounwind ssp uwtable {
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entry:
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%obj = alloca i64, align 8
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%f = inttoptr i64 281474417671919 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj)
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ret i64 %ret
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}
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; anyreg_test1
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; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
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; CHECK-NEXT: .short 0
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; 14 locations
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; CHECK-NEXT: .short 14
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 2: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 3: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 4: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 5: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 6: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 7: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 8: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 9: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 10: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 11: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 12: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 13: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
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entry:
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%f = inttoptr i64 281474417671919 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
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ret i64 %ret
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}
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; anyreg_test2
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; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
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; CHECK-NEXT: .short 0
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; 14 locations
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; CHECK-NEXT: .short 14
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 2: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 3: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 4: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 5: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 6: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 7: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 8: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 9: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 10: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 11: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 12: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 13: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
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entry:
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%f = inttoptr i64 281474417671919 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
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ret i64 %ret
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}
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; Test spilling the return value of an anyregcc call.
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;
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; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
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;
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; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 3
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; Loc 0: Register (some register that will be spilled to the stack)
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
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tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
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ret i64 %result
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}
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; Test spilling the arguments of an anyregcc call.
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;
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; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
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;
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; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 5
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; Loc 0: Return a register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Arg0 in a Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 2: Arg1 in a Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 3: Arg2 spilled to FP -96
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 29
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; CHECK-NEXT: .long -96
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; Loc 4: Arg3 spilled to FP - 88
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 29
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; CHECK-NEXT: .long -88
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define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
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%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
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ret i64 %result
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}
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declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
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declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
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