mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
3e16b022be
We've been performing the wrong operation on ARM for "atomicrmw nand" for years, since "a NAND b" is "~(a & b)" rather than ARM's very tempting "a & ~b". This bled over into the generic expansion pass. So I assume no-one has ever actually tried to do an atomic nand in the real world. Oh well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212443 91177308-0d34-0410-b5e6-96231b3b80d8
229 lines
8.3 KiB
LLVM
229 lines
8.3 KiB
LLVM
; RUN: llc < %s -march=arm64 -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone | FileCheck %s
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@var = global i128 0
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define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) {
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; CHECK-LABEL: val_compare_and_swap:
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxp [[RESULTLO:x[0-9]+]], [[RESULTHI:x[0-9]+]], [x[[ADDR:[0-9]+]]]
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; CHECK-DAG: eor [[MISMATCH_LO:x[0-9]+]], [[RESULTLO]], x2
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; CHECK-DAG: eor [[MISMATCH_HI:x[0-9]+]], [[RESULTHI]], x3
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; CHECK: orr [[MISMATCH:x[0-9]+]], [[MISMATCH_LO]], [[MISMATCH_HI]]
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; CHECK: cbnz [[MISMATCH]], [[DONE:.LBB[0-9]+_[0-9]+]]
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; CHECK: stxp [[SCRATCH_RES:w[0-9]+]], x4, x5, [x[[ADDR]]]
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; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]]
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; CHECK: [[DONE]]:
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%pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire
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%val = extractvalue { i128, i1 } %pair, 0
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ret i128 %val
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}
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define void @fetch_and_nand(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_nand:
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
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; CHECK-DAG: and [[TMP_REGLO:x[0-9]+]], [[DEST_REGLO]], x2
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; CHECK-DAG: and [[TMP_REGHI:x[0-9]+]], [[DEST_REGHI]], x3
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; CHECK-DAG: mvn [[SCRATCH_REGLO:x[0-9]+]], [[TMP_REGLO]]
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; CHECK-DAG: mvn [[SCRATCH_REGHI:x[0-9]+]], [[TMP_REGHI]]
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; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0]
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; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]]
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; CHECK-DAG: str [[DEST_REGHI]]
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; CHECK-DAG: str [[DEST_REGLO]]
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%val = atomicrmw nand i128* %p, i128 %bits release
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_or(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_or:
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
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; CHECK-DAG: orr [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2
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; CHECK-DAG: orr [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3
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; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0]
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; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]]
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; CHECK-DAG: str [[DEST_REGHI]]
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; CHECK-DAG: str [[DEST_REGLO]]
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%val = atomicrmw or i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_add(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_add:
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
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; CHECK: adds [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2
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; CHECK: adcs [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3
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; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0]
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; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]]
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; CHECK-DAG: str [[DEST_REGHI]]
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; CHECK-DAG: str [[DEST_REGLO]]
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%val = atomicrmw add i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_sub(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_sub:
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
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; CHECK: subs [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2
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; CHECK: sbcs [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3
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; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0]
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; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]]
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; CHECK-DAG: str [[DEST_REGHI]]
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; CHECK-DAG: str [[DEST_REGLO]]
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%val = atomicrmw sub i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_min(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_min:
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
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; CHECK: cmp [[DEST_REGLO]], x2
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; CHECK: cset [[LOCMP:w[0-9]+]], ls
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; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
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; CHECK: cset [[HICMP:w[0-9]+]], le
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; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
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; CHECK: cmp [[CMP]], #0
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; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
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; CHECK-DAG: csel [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2, ne
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; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0]
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; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]]
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; CHECK-DAG: str [[DEST_REGHI]]
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; CHECK-DAG: str [[DEST_REGLO]]
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%val = atomicrmw min i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_max(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_max:
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
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; CHECK: cmp [[DEST_REGLO]], x2
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; CHECK: cset [[LOCMP:w[0-9]+]], hi
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; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
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; CHECK: cset [[HICMP:w[0-9]+]], gt
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; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
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; CHECK: cmp [[CMP]], #0
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; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
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; CHECK-DAG: csel [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2, ne
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; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0]
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; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]]
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; CHECK-DAG: str [[DEST_REGHI]]
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; CHECK-DAG: str [[DEST_REGLO]]
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%val = atomicrmw max i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_umin(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_umin:
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
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; CHECK: cmp [[DEST_REGLO]], x2
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; CHECK: cset [[LOCMP:w[0-9]+]], ls
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; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
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; CHECK: cset [[HICMP:w[0-9]+]], ls
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; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
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; CHECK: cmp [[CMP]], #0
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; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
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; CHECK-DAG: csel [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2, ne
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; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0]
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; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]]
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; CHECK-DAG: str [[DEST_REGHI]]
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; CHECK-DAG: str [[DEST_REGLO]]
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%val = atomicrmw umin i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_umax(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_umax:
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
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; CHECK: cmp [[DEST_REGLO]], x2
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; CHECK: cset [[LOCMP:w[0-9]+]], hi
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; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
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; CHECK: cset [[HICMP:w[0-9]+]], hi
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; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
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; CHECK: cmp [[CMP]], #0
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; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
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; CHECK-DAG: csel [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2, ne
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; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0]
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; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]]
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; CHECK-DAG: str [[DEST_REGHI]]
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; CHECK-DAG: str [[DEST_REGLO]]
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%val = atomicrmw umax i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define i128 @atomic_load_seq_cst(i128* %p) {
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; CHECK-LABEL: atomic_load_seq_cst:
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; CHECK-NOT: dmb
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; CHECK-LABEL: ldaxp
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; CHECK-NOT: dmb
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%r = load atomic i128* %p seq_cst, align 16
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ret i128 %r
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}
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define i128 @atomic_load_relaxed(i128* %p) {
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; CHECK-LABEL: atomic_load_relaxed:
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; CHECK-NOT: dmb
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; CHECK: ldxp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x0]
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; CHECK-NOT: dmb
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%r = load atomic i128* %p monotonic, align 16
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ret i128 %r
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}
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define void @atomic_store_seq_cst(i128 %in, i128* %p) {
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; CHECK-LABEL: atomic_store_seq_cst:
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; CHECK-NOT: dmb
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxp xzr, xzr, [x2]
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; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
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; CHECK: cbnz [[SUCCESS]], [[LABEL]]
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; CHECK-NOT: dmb
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store atomic i128 %in, i128* %p seq_cst, align 16
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ret void
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}
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define void @atomic_store_release(i128 %in, i128* %p) {
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; CHECK-LABEL: atomic_store_release:
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; CHECK-NOT: dmb
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldxp xzr, xzr, [x2]
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; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
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; CHECK: cbnz [[SUCCESS]], [[LABEL]]
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; CHECK-NOT: dmb
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store atomic i128 %in, i128* %p release, align 16
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ret void
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}
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define void @atomic_store_relaxed(i128 %in, i128* %p) {
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; CHECK-LABEL: atomic_store_relaxed:
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; CHECK-NOT: dmb
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldxp xzr, xzr, [x2]
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; CHECK: stxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
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; CHECK: cbnz [[SUCCESS]], [[LABEL]]
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; CHECK-NOT: dmb
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store atomic i128 %in, i128* %p unordered, align 16
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ret void
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}
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