mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-22 09:29:31 +00:00
29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
236 lines
7.4 KiB
LLVM
236 lines
7.4 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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define i32 @test_rev_w(i32 %a) nounwind {
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entry:
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; CHECK-LABEL: test_rev_w:
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; CHECK: rev w0, w0
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%0 = tail call i32 @llvm.bswap.i32(i32 %a)
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ret i32 %0
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}
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define i64 @test_rev_x(i64 %a) nounwind {
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entry:
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; CHECK-LABEL: test_rev_x:
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; CHECK: rev x0, x0
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%0 = tail call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %0
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}
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declare i32 @llvm.bswap.i32(i32) nounwind readnone
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declare i64 @llvm.bswap.i64(i64) nounwind readnone
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define i32 @test_rev16_w(i32 %X) nounwind {
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entry:
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; CHECK-LABEL: test_rev16_w:
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; CHECK: rev16 w0, w0
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%tmp1 = lshr i32 %X, 8
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%X15 = bitcast i32 %X to i32
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%tmp4 = shl i32 %X15, 8
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%tmp2 = and i32 %tmp1, 16711680
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%tmp5 = and i32 %tmp4, -16777216
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%tmp9 = and i32 %tmp1, 255
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%tmp13 = and i32 %tmp4, 65280
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%tmp6 = or i32 %tmp5, %tmp2
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%tmp10 = or i32 %tmp6, %tmp13
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%tmp14 = or i32 %tmp10, %tmp9
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ret i32 %tmp14
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}
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; 64-bit REV16 is *not* a swap then a 16-bit rotation:
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; 01234567 ->(bswap) 76543210 ->(rotr) 10765432
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; 01234567 ->(rev16) 10325476
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define i64 @test_rev16_x(i64 %a) nounwind {
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entry:
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; CHECK-LABEL: test_rev16_x:
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; CHECK-NOT: rev16 x0, x0
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%0 = tail call i64 @llvm.bswap.i64(i64 %a)
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%1 = lshr i64 %0, 16
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%2 = shl i64 %0, 48
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%3 = or i64 %1, %2
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ret i64 %3
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}
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define i64 @test_rev32_x(i64 %a) nounwind {
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entry:
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; CHECK-LABEL: test_rev32_x:
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; CHECK: rev32 x0, x0
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%0 = tail call i64 @llvm.bswap.i64(i64 %a)
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%1 = lshr i64 %0, 32
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%2 = shl i64 %0, 32
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%3 = or i64 %1, %2
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ret i64 %3
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}
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define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: test_vrev64D8:
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;CHECK: rev64.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: test_vrev64D16:
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;CHECK: rev64.4h
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%tmp1 = load <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: test_vrev64D32:
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;CHECK: rev64.2s
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%tmp1 = load <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
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ret <2 x i32> %tmp2
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}
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define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
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;CHECK-LABEL: test_vrev64Df:
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;CHECK: rev64.2s
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%tmp1 = load <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
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ret <2 x float> %tmp2
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}
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define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: test_vrev64Q8:
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;CHECK: rev64.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: test_vrev64Q16:
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;CHECK: rev64.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: test_vrev64Q32:
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;CHECK: rev64.4s
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%tmp1 = load <4 x i32>* %A
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%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x i32> %tmp2
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}
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define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
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;CHECK-LABEL: test_vrev64Qf:
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;CHECK: rev64.4s
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%tmp1 = load <4 x float>* %A
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x float> %tmp2
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}
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define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: test_vrev32D8:
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;CHECK: rev32.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: test_vrev32D16:
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;CHECK: rev32.4h
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%tmp1 = load <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x i16> %tmp2
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}
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define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: test_vrev32Q8:
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;CHECK: rev32.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: test_vrev32Q16:
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;CHECK: rev32.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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ret <8 x i16> %tmp2
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}
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define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: test_vrev16D8:
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;CHECK: rev16.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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ret <8 x i8> %tmp2
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}
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define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: test_vrev16Q8:
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;CHECK: rev16.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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ret <16 x i8> %tmp2
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}
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; Undef shuffle indices should not prevent matching to VREV:
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define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: test_vrev64D8_undef:
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;CHECK: rev64.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
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ret <8 x i8> %tmp2
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}
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define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: test_vrev32Q16_undef:
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;CHECK: rev32.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
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ret <8 x i16> %tmp2
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}
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; vrev <4 x i16> should use REV32 and not REV64
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define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
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; CHECK-LABEL: test_vrev64:
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; CHECK: ldr [[DEST:q[0-9]+]],
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; CHECK: st1.h
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; CHECK: st1.h
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entry:
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%0 = bitcast <4 x i16>* %source to <8 x i16>*
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%tmp2 = load <8 x i16>* %0, align 4
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%tmp3 = extractelement <8 x i16> %tmp2, i32 6
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%tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0
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%tmp9 = extractelement <8 x i16> %tmp2, i32 5
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%tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1
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store <2 x i16> %tmp11, <2 x i16>* %dst, align 4
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ret void
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}
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; Test vrev of float4
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define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp {
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; CHECK: float_vrev64
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; CHECK: ldr [[DEST:q[0-9]+]],
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; CHECK: rev64.4s
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entry:
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%0 = bitcast float* %source to <4 x float>*
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%tmp2 = load <4 x float>* %0, align 4
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%tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
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%arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11
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store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
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ret void
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}
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define <4 x i32> @test_vrev32_bswap(<4 x i32> %source) nounwind {
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; CHECK-LABEL: test_vrev32_bswap:
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; CHECK: rev32.16b
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; CHECK-NOT: rev
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; CHECK: ret
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%bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %source)
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ret <4 x i32> %bswap
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}
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declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
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