mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-03 08:55:51 +00:00
159e7f4095
With VSX there is a real vector select instruction, and so we should use it. Note that VSELECT will still scalarize for v2f64 because the corresponding SetCC result type (v2i64) is not currently a legal type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204801 91177308-0d34-0410-b5e6-96231b3b80d8
278 lines
5.9 KiB
LLVM
278 lines
5.9 KiB
LLVM
; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define double @test1(double %a, double %b) {
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entry:
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%v = fmul double %a, %b
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ret double %v
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; CHECK-LABEL: @test1
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; CHECK: xsmuldp 1, 1, 2
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; CHECK: blr
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}
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define double @test2(double %a, double %b) {
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entry:
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%v = fdiv double %a, %b
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ret double %v
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; CHECK-LABEL: @test2
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; CHECK: xsdivdp 1, 1, 2
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; CHECK: blr
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}
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define double @test3(double %a, double %b) {
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entry:
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%v = fadd double %a, %b
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ret double %v
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; CHECK-LABEL: @test3
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; CHECK: xsadddp 1, 1, 2
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; CHECK: blr
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}
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define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
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entry:
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%v = fadd <2 x double> %a, %b
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ret <2 x double> %v
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; CHECK-LABEL: @test4
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; CHECK: xvadddp 34, 34, 35
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; CHECK: blr
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}
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define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%v = xor <4 x i32> %a, %b
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ret <4 x i32> %v
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; CHECK-LABEL: @test5
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; CHECK: xxlxor 34, 34, 35
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; CHECK: blr
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}
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define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%v = xor <8 x i16> %a, %b
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ret <8 x i16> %v
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; CHECK-LABEL: @test6
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; CHECK: xxlxor 34, 34, 35
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; CHECK: blr
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}
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define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%v = xor <16 x i8> %a, %b
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ret <16 x i8> %v
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; CHECK-LABEL: @test7
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; CHECK: xxlxor 34, 34, 35
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; CHECK: blr
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}
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define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%v = or <4 x i32> %a, %b
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ret <4 x i32> %v
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; CHECK-LABEL: @test8
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; CHECK: xxlor 34, 34, 35
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; CHECK: blr
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}
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define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%v = or <8 x i16> %a, %b
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ret <8 x i16> %v
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; CHECK-LABEL: @test9
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; CHECK: xxlor 34, 34, 35
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; CHECK: blr
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}
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define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%v = or <16 x i8> %a, %b
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ret <16 x i8> %v
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; CHECK-LABEL: @test10
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; CHECK: xxlor 34, 34, 35
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; CHECK: blr
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}
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define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%v = and <4 x i32> %a, %b
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ret <4 x i32> %v
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; CHECK-LABEL: @test11
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; CHECK: xxland 34, 34, 35
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; CHECK: blr
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}
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define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%v = and <8 x i16> %a, %b
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ret <8 x i16> %v
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; CHECK-LABEL: @test12
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; CHECK: xxland 34, 34, 35
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; CHECK: blr
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}
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define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%v = and <16 x i8> %a, %b
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ret <16 x i8> %v
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; CHECK-LABEL: @test13
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; CHECK: xxland 34, 34, 35
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; CHECK: blr
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}
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define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%v = or <4 x i32> %a, %b
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%w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %w
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; CHECK-LABEL: @test14
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; CHECK: xxlnor 34, 34, 35
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; CHECK: blr
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}
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define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%v = or <8 x i16> %a, %b
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%w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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ret <8 x i16> %w
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; CHECK-LABEL: @test15
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; CHECK: xxlnor 34, 34, 35
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; CHECK: blr
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}
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define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%v = or <16 x i8> %a, %b
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%w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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ret <16 x i8> %w
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; CHECK-LABEL: @test16
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; CHECK: xxlnor 34, 34, 35
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; CHECK: blr
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}
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define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
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%v = and <4 x i32> %a, %w
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ret <4 x i32> %v
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; CHECK-LABEL: @test17
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; CHECK: xxlandc 34, 34, 35
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; CHECK: blr
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}
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define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%v = and <8 x i16> %a, %w
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ret <8 x i16> %v
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; CHECK-LABEL: @test18
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; CHECK: xxlandc 34, 34, 35
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; CHECK: blr
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}
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define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%v = and <16 x i8> %a, %w
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ret <16 x i8> %v
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; CHECK-LABEL: @test19
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; CHECK: xxlandc 34, 34, 35
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; CHECK: blr
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}
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define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
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entry:
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%m = icmp eq <4 x i32> %c, %d
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%v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %v
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; CHECK-LABEL: @test20
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; CHECK: vcmpequw {{[0-9]+}}, 4, 5
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; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
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; CHECK: blr
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}
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define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
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entry:
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%m = fcmp oeq <4 x float> %c, %d
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%v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
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ret <4 x float> %v
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; CHECK-LABEL: @test21
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; CHECK: xvcmpeqsp [[V1:[0-9]+]], 36, 37
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; CHECK: xxsel 34, 35, 34, [[V1]]
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; CHECK: blr
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}
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define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
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entry:
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%m = fcmp ueq <4 x float> %c, %d
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%v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
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ret <4 x float> %v
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; CHECK-LABEL: @test22
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; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
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; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
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; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
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; CHECK-DAG: xxlnor
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; CHECK-DAG: xxlnor
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; CHECK-DAG: xxlor
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; CHECK-DAG: xxlor
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; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
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; CHECK: blr
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}
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define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
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entry:
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%m = icmp eq <8 x i16> %c, %d
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%v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %v
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; CHECK-LABEL: @test23
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; CHECK: vcmpequh {{[0-9]+}}, 4, 5
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; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
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; CHECK: blr
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}
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define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
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entry:
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%m = icmp eq <16 x i8> %c, %d
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%v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %v
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; CHECK-LABEL: @test24
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; CHECK: vcmpequb {{[0-9]+}}, 4, 5
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; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
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; CHECK: blr
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}
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define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
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entry:
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%m = fcmp oeq <2 x double> %c, %d
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%v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
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ret <2 x double> %v
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; CHECK-LABEL: @test25
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; FIXME: This currently is scalarized because v2i64 is not a legal type.
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; CHECK: blr
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}
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