.. |
AsmParser
|
Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.
|
2013-09-10 09:50:01 +00:00 |
Disassembler
|
This patch adds support for microMIPS disassembler and disassembler make check tests.
|
2013-09-06 12:30:36 +00:00 |
InstPrinter
|
[mips] Place parentheses around && to silence warning.
|
2013-09-07 00:26:26 +00:00 |
MCTargetDesc
|
Generate compact unwind encoding from CFI directives.
|
2013-09-09 02:37:14 +00:00 |
TargetInfo
|
|
|
CMakeLists.txt
|
Turn MipsOptimizeMathLibCalls into a target-independent scalar transform
|
2013-08-23 10:27:02 +00:00 |
LLVMBuild.txt
|
|
|
Makefile
|
|
|
MicroMipsInstrFormats.td
|
This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
|
2013-09-06 12:53:21 +00:00 |
MicroMipsInstrInfo.td
|
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
|
2013-09-07 00:02:02 +00:00 |
Mips16FrameLowering.cpp
|
|
|
Mips16FrameLowering.h
|
|
|
Mips16HardFloat.cpp
|
Make sure we don't generate stubs for any of these functions because they
|
2013-09-01 04:12:59 +00:00 |
Mips16HardFloat.h
|
|
|
Mips16InstrFormats.td
|
|
|
Mips16InstrInfo.cpp
|
|
|
Mips16InstrInfo.h
|
|
|
Mips16InstrInfo.td
|
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
|
2013-09-07 00:02:02 +00:00 |
Mips16ISelDAGToDAG.cpp
|
|
|
Mips16ISelDAGToDAG.h
|
|
|
Mips16ISelLowering.cpp
|
|
|
Mips16ISelLowering.h
|
|
|
Mips16RegisterInfo.cpp
|
|
|
Mips16RegisterInfo.h
|
|
|
Mips64InstrInfo.td
|
[mips] Add definition of instruction "drotr32" (double rotate right plus 32).
|
2013-09-07 00:18:01 +00:00 |
Mips.h
|
Turn MipsOptimizeMathLibCalls into a target-independent scalar transform
|
2013-08-23 10:27:02 +00:00 |
Mips.td
|
|
|
MipsAnalyzeImmediate.cpp
|
|
|
MipsAnalyzeImmediate.h
|
|
|
MipsAsmPrinter.cpp
|
|
|
MipsAsmPrinter.h
|
|
|
MipsCallingConv.td
|
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the
|
2013-08-20 23:38:40 +00:00 |
MipsCodeEmitter.cpp
|
[mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".
|
2013-09-06 23:52:46 +00:00 |
MipsCondMov.td
|
[mips] Set instruction itineraries of loads, stores and conditional moves.
|
2013-09-06 23:28:24 +00:00 |
MipsConstantIslandPass.cpp
|
|
|
MipsDelaySlotFiller.cpp
|
|
|
MipsDSPInstrFormats.td
|
|
|
MipsDSPInstrInfo.td
|
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
|
2013-09-07 00:02:02 +00:00 |
MipsFrameLowering.cpp
|
|
|
MipsFrameLowering.h
|
|
|
MipsInstrFormats.td
|
[mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
|
2013-09-06 23:40:15 +00:00 |
MipsInstrFPU.td
|
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
|
2013-09-07 00:52:30 +00:00 |
MipsInstrInfo.cpp
|
|
|
MipsInstrInfo.h
|
|
|
MipsInstrInfo.td
|
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
|
2013-09-07 00:02:02 +00:00 |
MipsISelDAGToDAG.cpp
|
[mips][msa] Added load/store intrinsics.
|
2013-08-28 12:04:29 +00:00 |
MipsISelDAGToDAG.h
|
[mips][msa] Added load/store intrinsics.
|
2013-08-28 12:04:29 +00:00 |
MipsISelLowering.cpp
|
Fix a problem with dual mips16/mips32 mode. When the underlying processor
|
2013-08-30 19:40:56 +00:00 |
MipsISelLowering.h
|
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
|
2013-09-07 00:52:30 +00:00 |
MipsJITInfo.cpp
|
|
|
MipsJITInfo.h
|
|
|
MipsLongBranch.cpp
|
|
|
MipsMachineFunction.cpp
|
|
|
MipsMachineFunction.h
|
|
|
MipsMCInstLower.cpp
|
|
|
MipsMCInstLower.h
|
|
|
MipsModuleISelDAGToDAG.cpp
|
|
|
MipsModuleISelDAGToDAG.h
|
|
|
MipsMSAInstrFormats.td
|
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v
|
2013-08-28 12:14:50 +00:00 |
MipsMSAInstrInfo.td
|
[mips][msa] Removed unsupported dot product instructions (dotp_[su].b)
|
2013-09-10 09:51:43 +00:00 |
MipsOs16.cpp
|
|
|
MipsOs16.h
|
|
|
MipsRegisterInfo.cpp
|
[mips][msa] Added cfcmsa, and ctcmsa
|
2013-08-28 10:26:24 +00:00 |
MipsRegisterInfo.h
|
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
|
2013-08-20 21:08:22 +00:00 |
MipsRegisterInfo.td
|
[mips][msa] Added cfcmsa, and ctcmsa
|
2013-08-28 10:26:24 +00:00 |
MipsRelocations.h
|
|
|
MipsSchedule.td
|
|
|
MipsSEFrameLowering.cpp
|
[mips] Define register class FGRH32 for the high half of the 64-bit floating
|
2013-08-20 22:58:56 +00:00 |
MipsSEFrameLowering.h
|
|
|
MipsSEInstrInfo.cpp
|
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
|
2013-09-07 00:52:30 +00:00 |
MipsSEInstrInfo.h
|
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
|
2013-09-07 00:52:30 +00:00 |
MipsSEISelDAGToDAG.cpp
|
[mips][msa] Added load/store intrinsics.
|
2013-08-28 12:04:29 +00:00 |
MipsSEISelDAGToDAG.h
|
[mips][msa] Added load/store intrinsics.
|
2013-08-28 12:04:29 +00:00 |
MipsSEISelLowering.cpp
|
[mips] When double precision loads and stores are split into two i32 loads and
|
2013-09-09 17:59:32 +00:00 |
MipsSEISelLowering.h
|
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
|
2013-09-07 00:52:30 +00:00 |
MipsSelectionDAGInfo.cpp
|
|
|
MipsSelectionDAGInfo.h
|
|
|
MipsSERegisterInfo.cpp
|
|
|
MipsSERegisterInfo.h
|
|
|
MipsSubtarget.cpp
|
Fix a problem with dual mips16/mips32 mode. When the underlying processor
|
2013-08-30 19:40:56 +00:00 |
MipsSubtarget.h
|
Fix a problem with dual mips16/mips32 mode. When the underlying processor
|
2013-08-30 19:40:56 +00:00 |
MipsTargetMachine.cpp
|
Turn MipsOptimizeMathLibCalls into a target-independent scalar transform
|
2013-08-23 10:27:02 +00:00 |
MipsTargetMachine.h
|
|
|
MipsTargetObjectFile.cpp
|
|
|
MipsTargetObjectFile.h
|
|
|