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https://github.com/c64scene-ar/llvm-6502.git
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1617e6c997
imply types of SSA Registers. This is on a per-function basis, so the MachineFunction contains the SSARegMap, and has accessor functions to it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4774 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.2 KiB
C++
41 lines
1.2 KiB
C++
//===-- llvm/CodeGen/SSARegMap.h --------------------------------*- C++ -*-===//
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//
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// Map register numbers to register classes that are correctly sized (typed) to
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// hold the information. Assists register allocation. Contained by
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// MachineFunction, should be deleted by register allocator when it is no
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// longer needed.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SSAREGMAP_H
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#define LLVM_CODEGEN_SSAREGMAP_H
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#include "llvm/Target/MRegisterInfo.h"
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class TargetRegisterClass;
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class SSARegMap {
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std::vector<const TargetRegisterClass*> RegClassMap;
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unsigned rescale(unsigned Reg) {
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return Reg - MRegisterInfo::FirstVirtualRegister;
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}
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public:
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SSARegMap() {}
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const TargetRegisterClass* getRegClass(unsigned Reg) {
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unsigned actualReg = rescale(Reg);
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assert(actualReg < RegClassMap.size() && "Register out of bounds");
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return RegClassMap[actualReg];
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}
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void addRegMap(unsigned Reg, const TargetRegisterClass* RegClass) {
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assert(rescale(Reg) == RegClassMap.size() &&
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"Register mapping not added in sequential order!");
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RegClassMap.push_back(RegClass);
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}
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};
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#endif
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